公开(公告)号：DE102004019090B4

公开(公告)日：2006-05-04

申请号：DE102004019090

申请日：2004-04-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L27/08 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: Trench capacitor comprises a trench (2) formed in a semiconductor substrate (1), an insulating collar (5'') in the upper region of the trench, a lower metallic capacitor electrode (100'') arranged in the trench on the substrate, an upper conducting capacitor electrode (100''') arranged in the trench and a dielectric layer (70) as capacitor dielectric arranged between the first and second capacitor electrode. The lower capacitor electrode has a stoichiometric composition varying from the substrate to the dielectric layer from a first value (C1) to a second value (C2). - An INDEPENDENT CLAIM is also included for: a process for the production of a trench capacitor.

公开(公告)号：DE102004007410B4

公开(公告)日：2006-01-19

申请号：DE102004007410

申请日：2004-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

Abstract: The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate ( 101 ), which forms a first electrode, a trench-like recess ( 102 ) etched into the substrate ( 101 ), conductive material, which is provided as a projection in a central region of the trench-like recess ( 102 ) and spaced apart from the side walls ( 107 ) of the trench-like recess ( 102 ) and is in electrical contact with the substrate at the base ( 104 ) of the trench-like recess ( 102 ), a dielectric layer ( 108 ), which has been deposited on the side walls ( 107 ) of the trench-like recess ( 102 ), the base ( 104 ) of the trench-like recess ( 102 ) and the surfaces of the conductive material ( 105 ), and an electrode layer ( 110 ), which has been deposited on the dielectric layer ( 108 ) and forms a second electrode.

公开(公告)号：DE102004023805A1

公开(公告)日：2005-12-08

申请号：DE102004023805

申请日：2004-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ULRICH ,  SEIDL HARALD

IPC: H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/08 ,  H01L29/94

Abstract: The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate ( 1; 1', 60, 1 '') having a front side (VS) and a rear side (RS); providing trenches ( 5 ) in the semiconductor substrate ( 1; 1', 60, 1 '') proceeding from the front side (VS) of the semiconductor substrate ( 1; 1', 60, 1 ''); providing a respective inner capacitor electrode ( 6 ) in the trenches ( 5 ); uncovering the inner capacitor electrodes ( 6 ) proceeding from the rear side (RS) of the semiconductor substrate ( 1; 1', 60, 1 ''); providing a capacitor dielectric ( 40 ) on the uncovered inner capacitor electrodes ( 6 ); and providing outer capacitor electrodes ( 50 ) on the capacitor dielectric ( 40 ) on the inner capacitor electrodes ( 6 ).

公开(公告)号：DE102004040797A1

公开(公告)日：2005-10-20

申请号：DE102004040797

申请日：2004-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ULRICH

IPC: C23C16/30 ,  C23C16/38 ,  C23C16/455 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768

Abstract: Forming layers on a substrate (100) comprises placing the substrate in a reactor, precipitating a precursor layer (101a-n) composed of a primary material, flushing the layer system with a gas, and then precipitating a second precursor layer (102a-n) on top. The layer system formed is flushed with a gas, and the precipitation steps are repeated until the desired thickness is achieved.

公开(公告)号：DE10345475A1

公开(公告)日：2005-05-04

申请号：DE10345475

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  HAPP THOMAS ,  PINNOW CAY-UWE ,  GUTSCHE MARTIN

IPC: G03G15/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

公开(公告)号：DE10248980A1

公开(公告)日：2004-05-06

申请号：DE10248980

申请日：2002-10-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: C23C16/02 ,  C23C16/04 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

Abstract: Production of structured silicon dioxide layers on process surfaces arranged perpendicular or slanted towards a substrate surface comprises preparing a substrate (4) with a relief in a process chamber, forming a starter layer (17) with leaving groups substituted by hydroxyl groups on sections of the process surfaces which extend from the substrate surface up to a determined covering depth of the relief, and applying tris(tert.-butoxy)silanol to the substrate so that a silicon dioxide layer (18) is selectively grown on the starter layer.

公开(公告)号：DE10208450A1

公开(公告)日：2003-09-11

申请号：DE10208450

申请日：2002-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE ,  SELL BERNHARD ,  SEIDL HARALD ,  HECHT THOMAS ,  GUTSCHE MARTIN

IPC: C23C16/34 ,  C23C16/40 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C23C16/46 ,  C23C16/48 ,  C23C16/30

Abstract: Process chamber for producing a layer of material on sections of a surface (8) of a substrate (3) comprises: holding unit (2) for substrate; feeding and removal units (6) for gas phases of chemical precursors of the layer material; substrate feeding device (11) for introducing substrate into process chamber; heating source (9) for heating the substrate and/or substrate surface; and control unit. The control unit is used for sequentially introducing the chemical precursor compounds. The heating source (9) is formed as a radiation source, by means of which the temperature on the substrate surface can be changed in steps of more than 100 K per second. The radiation source is a heating lamp and is arranged in the chamber inner chamber (5) of the process chamber enclosed by a chamber wall (4). An Independent claim is also included for a process for depositing a layer of material on sections of a surface of a substrate.

公开(公告)号：DE10142580A1

公开(公告)日：2003-03-27

申请号：DE10142580

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ,  HECHT THOMAS ,  LEONHARDT MATTHIAS ,  SCHROEDER UWE

IPC: H01L21/8242

公开(公告)号：DE10143650A1

公开(公告)日：2003-03-13

申请号：DE10143650

申请日：2001-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  LUETZEN JOERN ,  POPP MARTIN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory cell has trenches (25,50) in a substrate (15) having a capacitor (30) and long trenches having spacer wordlines with an active region between them having a vertical select transistor. Conductive bridges between wordlines in a trench are less than half as thick as the trench width. An Independent claim is also included for a process for making the above memory.

公开(公告)号：DE10345475B4

公开(公告)日：2008-04-17

申请号：DE10345475

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  HAPP THOMAS ,  PINNOW CAY-UWE ,  GUTSCHE MARTIN

IPC: H01L27/115 ,  G03G15/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.