公开(公告)号：HK1036150A1

公开(公告)日：2001-12-21

申请号：HK01106779

申请日：2001-09-26

Applicant: IBM ,  SIEMENS AG

Inventor： CLEVENGER LARRY ,  FILIPPI RONALD G ,  GAMBINO JEFFREY ,  GIGNAC LYNNE ,  HURD JEFFERY L ,  HOINKIS MARK ,  IGGULDEN ROY C ,  MEHTER EBRAHIM ,  RODBELL KENNETH P ,  SCHNABEL FLORIAN ,  WEBER STEFAN J

IPC: H01L20060101 ,  H01L

公开(公告)号：DE60332865D1

公开(公告)日：2010-07-15

申请号：DE60332865

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

公开(公告)号：AT470237T

公开(公告)日：2010-06-15

申请号：AT03796085

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：DE102004028026B4

公开(公告)日：2006-08-10

申请号：DE102004028026

申请日：2004-06-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUMAR KAUSHIK ,  CLEVENGER LARRY ,  DALTON TIMOTHY J ,  LA TULIPE DOUGLAS C ,  COWLEY ANDY ,  KALTALIOGLU ERDEM ,  SCHACHT JOCHEN ,  HOINKIS MARK ,  SIMON ANDREW H ,  KALDOR STEFFEN ,  YANG CHIH-CHAO

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

公开(公告)号：DE102004028026A1

公开(公告)日：2005-02-03

申请号：DE102004028026

申请日：2004-06-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUMAR KAUSHIK ,  CLEVENGER LARRY ,  DALTON TIMOTHY J ,  LA TULIPE DOUGLAS C ,  COWLEY ANDY ,  KALTALIOGLU ERDEM ,  SCHACHT JOCHEN ,  HOINKIS MARK ,  SIMON ANDREW H ,  KALDOR STEFFEN ,  YANG CHIH-CHAO

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213

公开(公告)号：AU2003273328A8

公开(公告)日：2004-04-08

申请号：AU2003273328

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.