公开(公告)号：EP2798476A4

公开(公告)日：2016-06-29

申请号：EP11878535

申请日：2011-12-30

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  SAIR SULEYMAN ,  DOSHI KSHITIJ A ,  YOUNT CHARLES R ,  TOLL BRET L

IPC: G06F9/30 ,  G06F9/305 ,  H03M7/46

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  H03M7/46 ,  H03M7/6005

Abstract: A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.

Abstract translation: 包括硬件解码单元和执行引擎单元的处理器核心。 用于解码向量频率扩展指令的硬件解码单元，其中所述向量频率压缩指令包括源操作数和目的地操作数，其中所述源操作数指定源向量寄存器，其包括一对或多对值和游程长度， 根据运行长度将其扩展为该值的运行。 执行引擎单元执行解码的向量频率扩展指令，其使得源向量寄存器中的一个或多个源数据元素的集合被扩展为包括比该源数据元素集合更多的元素的一组目的地数据元素，以及 包括在源向量寄存器中运行长度编码的至少一个相同值的运行。

公开(公告)号：EP3238026A4

公开(公告)日：2018-08-01

申请号：EP15873962

申请日：2015-11-23

Applicant: INTEL CORP

Inventor： JHA ASHISH ,  VALENTINE ROBERT ,  OULD-AHMED-VALL ELMOUSTAPHA

IPC: G06F9/30 ,  G06F12/02

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30101 ,  G06F15/8053

Abstract: An apparatus and method for performing vector index loads and stores. For example, one embodiment of a processor comprises: a vector index register to store a plurality of index values; a mask register to store a plurality of mask bits; a vector register to store a plurality of vector data elements loaded from memory; and vector index load logic to identify an index stored in the vector index register to be used for a load operation using an immediate value and to responsively combine the index with a base memory address to determine a memory address for the load operation, the vector index load logic to load vector data elements from the memory address to the vector register in accordance with the plurality of mask bits.

公开(公告)号：EP3218814A4

公开(公告)日：2018-07-18

申请号：EP15858739

申请日：2015-10-14

Applicant: INTEL CORP

Inventor： EVANS ARNOLD KERRY ,  OULD-AHMED-VALL ELMOUSTAPHA

IPC: G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145

Abstract: A processor includes packed data registers, a decode unit, and an execution unit. The decode unit is to decode a four-dimensional (4D) Morton coordinate conversion instruction. The 4D Morton coordinate conversion instruction is to indicate a source packed data operand that is to include a plurality of 4D Morton coordinates, and is to indicate one or more destination storage locations. The execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the decode unit decoding the 4D Morton coordinate conversion instruction, is to store one or more result packed data operands in the one or more destination storage locations. The one or more result packed data operands are to include a plurality of sets of four 4D coordinates. Each of the sets of the four 4D coordinates is to correspond to a different one of the 4D Morton coordinates.

公开(公告)号：EP2695054A4

公开(公告)日：2017-05-31

申请号：EP11862801

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： VALENTINE ROBERT C ,  SAN ADRIAN JESUS CORBAL ,  SANS ROGER ESPASA ,  CAVIN ROBERT D ,  TOLL BRET L ,  DURAN SANTIAGO GALAN ,  WIEDEMEIER JEFFREY G ,  SAMUDRALA SRIDHAR ,  GIRKAR MILIND BABURAO ,  GROCHOWSKI EDWARD THOMAS ,  HALL JONATHAN CANNON ,  BRADFORD DENNIS R ,  OULD-AHMED-VALL ELMOUSTAPHA ,  ABEL JAMES C ,  CHARNEY MARK ,  ABRAHAM SETH ,  SAIR SULEYMAN ,  FORSYTH ANDREW THOMAS ,  YOUNT CHARLES ,  WU LISA

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305

CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract translation: 矢量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 该指令集包括一个矢量友好的指令格式。 矢量友好指令格式具有多个字段，包括基本操作字段，修饰符字段，扩充操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同扩充操作，通过放置 基础操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中可以仅将不同值中的一个置于基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现处的alpha字段，beta字段和数据元素宽度字段。

公开(公告)号：EP2798478A4

公开(公告)日：2016-12-21

申请号：EP11878962

申请日：2011-12-30

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  SAIR SULEYMAN ,  DOSHI KSHITIJ A ,  YOUNT CHARLES R ,  TOLL BRET L

IPC: G06F9/30 ,  G06F9/305 ,  H03M7/46

CPC classification number: G06F9/30018 ,  G06F9/30036 ,  H03M7/46

Abstract: A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.

公开(公告)号：EP2798465A4

公开(公告)日：2016-07-06

申请号：EP11878889

申请日：2011-12-30

Applicant: INTEL CORP

Inventor： PLOTNIKOV MIKHAIL ,  NARALKIN ANDREY ,  OULD-AHMED-VALL ELMOUSTAPHA ,  SHALNOV SERGEY

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/4552

Abstract: A method of an aspect includes receiving a unique packed data element identification instruction. The unique packed data element identification instruction indicates a source packed data having a plurality of packed data elements and indicates a destination storage location. A unique packed data element identification result is stored in the destination storage location in response to the unique packed data element identification instruction. The unique packed data element identification result indicates which of the plurality of the packed data elements are unique in the source packed data. Other methods, apparatus, systems, and instructions are disclosed.

Abstract translation: 一个方面的方法包括：接收唯一打包数据元素标识指令。 独特的打包数据元素标识指令指示具有打包数据元素的多个A源打包数据和指示目的地存储位置。 一个独特的打包数据元素标识结果存储在目的地存储位置响应于所述唯一打包数据元素标识指令。 独特的打包数据元素识别结果表示打包数据元素的多个哪些是在源打包数据是唯一的。 其他的方法，设备，系统和指令游离缺失盘。

公开(公告)号：EP3238024A4

公开(公告)日：2018-07-25

申请号：EP15873912

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  CORBAL SAN ADRIAN JESUS ,  CHARNEY MARK J

IPC: G06F9/30 ,  G06F7/76

CPC classification number: G06F9/30185 ,  G06F7/76 ,  G06F7/764 ,  G06F9/30018 ,  G06F9/30032

Abstract: In one embodiment a processing device implements a set of instructions to perform an inverse centrifuge operation using vector or general purpose registers. The inverse centrifuge operation interleaves bits from opposite regions of a source and writes the interleaved bits to a destination. The instructions use a control mask where each bit with a mask value of one is obtained from one side of the source register or vector elements with a mask of zero are obtained from the opposing side.

公开(公告)号：EP3218815A4

公开(公告)日：2018-07-18

申请号：EP15859106

申请日：2015-10-14

Applicant: INTEL CORP

Inventor： EVANS ARNOLD KERRY ,  OULD-AHMED-VALL ELMOUSTAPHA

IPC: G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3016

Abstract: A processor includes a plurality of packed data registers, a decode unit, and an execution unit. The decode unit is to decode a three-dimensional (3D) Morton coordinate conversion instruction. The 3D Morton coordinate conversion instruction to indicate a source packed data operand that is to include a plurality of 3D Morton coordinates, and to indicate one or more destination storage locations. The execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the decode unit decoding the 3D Morton coordinate conversion instruction, is to store one or more result packed data operands in the one or more destination storage locations. The one or more result packed data operands are to include a plurality of sets of three 3D coordinates. Each of the sets of the three 3D coordinates is to correspond to a different one of the 3D Morton coordinates.

公开(公告)号：EP3238031A4

公开(公告)日：2018-06-27

申请号：EP15873977

申请日：2015-11-23

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  TOLL BRET L ,  CORBAL SAN ADRIAN JESUS ,  CHARNEY MARK J ,  GIRKAR MILIND B

IPC: G06F9/30 ,  G06F7/485 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F17/16

Abstract: In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.

公开(公告)号：EP3198227A4

公开(公告)日：2018-05-30

申请号：EP15843934

申请日：2015-08-25

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  CHERUVU SUNIL K

IPC: G01C21/26 ,  G01C21/34 ,  G01C21/36 ,  G08G1/01 ,  G08G1/0968

CPC classification number: G01C21/3415 ,  G01C21/3492 ,  G01C21/3691 ,  G08G1/0112 ,  G08G1/0133 ,  G08G1/0141 ,  G08G1/096827 ,  G08G1/096844

Abstract: Technologies for sharing route navigation data in a community cloud include a mobile navigation device of a vehicle and a remote mobile navigation device of a remote vehicle. The mobile navigation device generates sensor data associated with a current route of the vehicle and determines whether a reference traffic event occurs within a segment of the current route of the vehicle. In response to a determination that a reference traffic event occurs, the mobile navigation devices transmits route update data to the remote mobile navigation device. Based on the route update data, the remote mobile navigation device updates a current route of the remote vehicle to avoid the reference traffic event within a corresponding segment of the current route of the remote vehicle. The mobile navigation device may also transmit the sensor data to a community compute device, which may transmit route update data to the remote mobile navigation device.