公开(公告)号：DE102008016533A1

公开(公告)日：2008-11-13

申请号：DE102008016533

申请日：2008-03-31

Applicant: INTEL CORP

Inventor： TANG PING TAK PETER ,  CAVIN ROBERT D

IPC: G06F7/57

Abstract: A new function for calculating the reciprocal residual of a floating-point number X is defined as recip_residual(X)=1−X*recip(X), where recip(X) represents the reciprocal of X. The function may be implemented using a fused multiply-add unit in a processor. The reciprocal value of X, recip(X), may be obtained from a lookup table. The recip_residual function may help reduce the latency of many multiplicative functions that are based on products of multiple numbers and can be expressed in simple terms of functions on each individual number (e.g., log(U*V)=log(U)+log(V)).

公开(公告)号：DE102008059790A1

公开(公告)日：2009-07-02

申请号：DE102008059790

申请日：2008-12-01

Applicant: INTEL CORP

Inventor： CAVIN ROBERT D

IPC: G06F9/315 ,  G06F9/312

Abstract: A computer processor includes control logic for executing LoadUnpack and PackStore instructions. In one embodiment, the processor includes a vector register and a mask register. In response to a PackStore instruction with an argument specifying a memory location, a circuit in the processor copies unmasked vector elements from the vector register to consecutive memory locations, starting at the specified memory location, without copying masked vector elements. In response to a LoadUnpack instruction, the circuit copies data items from consecutive memory locations, starting at an identified memory location, into unmasked vector elements of the vector register, without copying data to masked vector elements. Other embodiments are described and claimed.

公开(公告)号：GB2502936A

公开(公告)日：2013-12-11

申请号：GB201317902

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： VALENTINE ROBERT ,  ADRIAN JESUS CORBAL SAN ,  SANS ROGER ESPASA ,  CAVIN ROBERT D ,  TOLL BRET L ,  DURAN SANTIAGO GALAN ,  WIEDEMEIER JEFFREY ,  SAMUDRALA SRIDHAR ,  GIRKAR MILIND BABURAO ,  GROCHOWSKI EDWARD THOMAS ,  HALL JONATHAN CANNON ,  BRADFORD DENNIS R ,  OULD-AHMED-VALL ELMOUSTAPHA ,  ABEL JAMES C ,  CHARNEY MARK J ,  ABRAHAM SETH ,  SAIR SULEYMAN ,  FORSYTH ANDREW THOMAS ,  YOUNT CHARLES ,  WU LISA K

IPC: G06F15/80 ,  G06F9/30

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：EP2695054A4

公开(公告)日：2017-05-31

申请号：EP11862801

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： VALENTINE ROBERT C ,  SAN ADRIAN JESUS CORBAL ,  SANS ROGER ESPASA ,  CAVIN ROBERT D ,  TOLL BRET L ,  DURAN SANTIAGO GALAN ,  WIEDEMEIER JEFFREY G ,  SAMUDRALA SRIDHAR ,  GIRKAR MILIND BABURAO ,  GROCHOWSKI EDWARD THOMAS ,  HALL JONATHAN CANNON ,  BRADFORD DENNIS R ,  OULD-AHMED-VALL ELMOUSTAPHA ,  ABEL JAMES C ,  CHARNEY MARK ,  ABRAHAM SETH ,  SAIR SULEYMAN ,  FORSYTH ANDREW THOMAS ,  YOUNT CHARLES ,  WU LISA

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305

CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract translation: 矢量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 该指令集包括一个矢量友好的指令格式。 矢量友好指令格式具有多个字段，包括基本操作字段，修饰符字段，扩充操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同扩充操作，通过放置 基础操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中可以仅将不同值中的一个置于基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现处的alpha字段，beta字段和数据元素宽度字段。