公开(公告)号：JP2005025718A

公开(公告)日：2005-01-27

申请号：JP2003425711

申请日：2003-12-22

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： ABEL JAMES C ,  WALTERS DERIN C ,  TYLER JONATHAN J

IPC: G06F7/38 ,  G06F5/01 ,  G06F7/496 ,  G06F7/52 ,  G06F7/523 ,  G06F7/53 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F9/30014 ,  G06F5/01 ,  G06F7/49947 ,  G06F7/5338 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/382 ,  G06F2207/3828

Abstract: PROBLEM TO BE SOLVED: To provide a method, a device and a system for performing a packed multiply high with round and shift processing, and to provide a machine readable medium. SOLUTION: The method comprises: a step for receiving a 1st operand having a 1st set of L data elements; a step for receiving a 2nd operand having a 2nd set of L data elements; a step for generating a set of L products by mutually multiplying L data element pairs each of which has the 1st data element from the 1st set of L data elements and the 2nd data element from a corresponding data element position of the 2nd set consisting of L data elements, a step for generating L rounded values by respectively rounding the L products, a step for generating L scaled values by respectively scaling the L rounded values; and a step for performing the round-off processing of each of the L scaled values so as to store the round-off value in a data element position corresponding to the pair of the data element. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于执行带有轮换和换档处理的打包乘法的方法，装置和系统，并且提供机器可读介质。 解决方案：该方法包括：接收具有第一组L个数据元素的第一操作数的步骤; 接收具有第二组L个数据元素的第二操作数的步骤; 通过将来自第一组L个数据元素的第一数据元素和来自第二组的对应数据元素位置的第二数据元素相互相乘的L个数据元素对相互相乘来生成一组L个乘积的步骤 数据元素，通过分别对L个乘积舍入来产生L个舍入值的步骤，分别缩放L个舍入值来产生L个缩放值的步骤; 以及执行对L个缩放值中的每一个的舍入处理以便将舍入值存储在与该对数据元素对应的数据元素位置中的步骤。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：GB2502936A

公开(公告)日：2013-12-11

申请号：GB201317902

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： VALENTINE ROBERT ,  ADRIAN JESUS CORBAL SAN ,  SANS ROGER ESPASA ,  CAVIN ROBERT D ,  TOLL BRET L ,  DURAN SANTIAGO GALAN ,  WIEDEMEIER JEFFREY ,  SAMUDRALA SRIDHAR ,  GIRKAR MILIND BABURAO ,  GROCHOWSKI EDWARD THOMAS ,  HALL JONATHAN CANNON ,  BRADFORD DENNIS R ,  OULD-AHMED-VALL ELMOUSTAPHA ,  ABEL JAMES C ,  CHARNEY MARK J ,  ABRAHAM SETH ,  SAIR SULEYMAN ,  FORSYTH ANDREW THOMAS ,  YOUNT CHARLES ,  WU LISA K

IPC: G06F15/80 ,  G06F9/30

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：EP2695054A4

公开(公告)日：2017-05-31

申请号：EP11862801

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： VALENTINE ROBERT C ,  SAN ADRIAN JESUS CORBAL ,  SANS ROGER ESPASA ,  CAVIN ROBERT D ,  TOLL BRET L ,  DURAN SANTIAGO GALAN ,  WIEDEMEIER JEFFREY G ,  SAMUDRALA SRIDHAR ,  GIRKAR MILIND BABURAO ,  GROCHOWSKI EDWARD THOMAS ,  HALL JONATHAN CANNON ,  BRADFORD DENNIS R ,  OULD-AHMED-VALL ELMOUSTAPHA ,  ABEL JAMES C ,  CHARNEY MARK ,  ABRAHAM SETH ,  SAIR SULEYMAN ,  FORSYTH ANDREW THOMAS ,  YOUNT CHARLES ,  WU LISA

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305

CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract translation: 矢量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 该指令集包括一个矢量友好的指令格式。 矢量友好指令格式具有多个字段，包括基本操作字段，修饰符字段，扩充操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同扩充操作，通过放置 基础操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中可以仅将不同值中的一个置于基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现处的alpha字段，beta字段和数据元素宽度字段。