公开(公告)号：WO2004079783A3

公开(公告)日：2005-01-20

申请号：PCT/US2004005944

申请日：2004-02-26

Applicant: LAM RES CORP ,  DEL PUPPO HELENE ,  LIN FRANK ,  LEE CHRIS ,  VAHEDI VAHID ,  KAMP THOMAS A ,  MILLER ALAN J

Inventor： DEL PUPPO HELENE ,  LIN FRANK ,  LEE CHRIS ,  VAHEDI VAHID ,  KAMP THOMAS A ,  MILLER ALAN J

IPC: H01L21/3213 ,  H01L21/302

CPC classification number: H01L21/32137

Abstract: A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Abstract translation: 提供了一种在等离子体蚀刻室中蚀刻多晶硅栅极结构的方法。 该方法开始于限定保护待蚀刻的多晶硅膜的图案。 然后，产生等离子体。 接下来，蚀刻大部分未被保护的多晶硅膜。 然后，引入含硅气体，并且在引入含硅气体的同时蚀刻剩余的多晶硅膜。 还提供了一种被配置为在蚀刻工艺期间引入含硅气体的蚀刻室。

公开(公告)号：JP2006074046A

公开(公告)日：2006-03-16

申请号：JP2005249201

申请日：2005-08-30

Applicant: Lam Res Corp ,  ラム リサーチ コーポレーションLam Research Corporation

Inventor： COOPERBERG DAVID ,  VAHEDI VAHID

IPC: H01L21/3065 ,  H05H1/46

Abstract: PROBLEM TO BE SOLVED: To provide an extension method for a process and profile simulator algorithm used for predicting a surface profile created by a known plasma treatment. SOLUTION: This extension method for the process and profile simulator algorithm predicts the surface profile generated by a given plasma process. First, high-energy particles are tracked. After that, an ion flux generated by the high-energy particles is recorded. Local etching speed and local deposit rate are calculated from the types of neutral flux, surface chemical coverage and surface materials that are solved simultaneously. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于预测由已知等离子体处理产生的表面轮廓的过程和轮廓模拟器算法的扩展方法。 解决方案：该扩展方法用于过程和轮廓模拟器算法预测由给定等离子体过程产生的表面轮廓。 首先，跟踪高能粒子。 之后，记录高能粒子产生的离子通量。 局部蚀刻速度和局部沉积速率根据同时求解的中性通量，表面化学覆盖率和表面材料的类型计算。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2010282636A

公开(公告)日：2010-12-16

申请号：JP2010156714

申请日：2010-07-09

Applicant: Lam Res Corp ,  ラム リサーチ コーポレイション

Inventor： BARONE MARIA E ,  GOTTSCHO RICHARD A ,  VAHEDI VAHID

IPC: C23C14/54 ,  G06Q10/00 ,  C23C16/52 ,  H01J37/32 ,  H01L21/205 ,  H01L21/3065

CPC classification number: H01J37/32935

Abstract: PROBLEM TO BE SOLVED: To provide a method for predicting a processing surface profile predicting a process surface profile that a given plasma process will create on a process substrate. SOLUTION: In this method, test values of input variables are selected (200), plasma is modeled (210), results of a test process of the substrate surface profile are substantially predicted by using the result in 210 and substrate parameters given in 200 (220), initial values of the surface profile model related to the input variables and unknown coefficients are obtained (230), instructions for difference between the test surface profile and the substantial profile predicted value are generated, and optimum values of unknown coefficients for minimizing the instructions for difference are generated. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种预测处理表面轮廓的方法，该处理表面轮廓预测给定等离子体处理将在处理衬底上产生的工艺表面轮廓。

解决方案：在此方法中，选择输入变量的测试值（200），对等离子体进行建模（210），通过使用210中的结果和给定的衬底参数，基本上预测了衬底表面轮廓的测试过程的结果 在200（220）中，获得与输入变量和未知系数相关的表面轮廓模型的初始值（230），产生测试表面轮廓和实际轮廓预测值之间的差异指令，并且产生未知系数的最佳值 生成差异指令的最小化。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：AT362652T

公开(公告)日：2007-06-15

申请号：AT03728281

申请日：2003-03-25

Applicant: LAM RES CORP

Inventor： KAMP TOM ,  GOTTSCHO RICHARD ,  LEE STEVE ,  LEE CHRIS ,  YAMAGUCHI YOKO ,  VAHEDI VAHID ,  EPPLER AARON

IPC: H01L21/3065 ,  H01L21/324 ,  H01L21/00 ,  H01L21/311 ,  H01L21/68 ,  H01L21/683 ,  H01L21/768

Abstract: An etch processor for etching a wafer includes a chuck for holding the wafer and a temperature sensor reporting a temperature of the wafer. The chuck includes a heater controlled by a temperature control system. The temperature sensor is operatively coupled to the temperature control system to maintain the temperature of the chuck at a selectable setpoint temperature. A first setpoint temperature and a second setpoint temperature are selected. The wafer is placed on the chuck and set to the first setpoint temperature. The wafer is then processed for a first period of time at the first setpoint temperature and for a second period of time at the second setpoint temperature.

公开(公告)号：DE69924834T2

公开(公告)日：2006-02-23

申请号：DE69924834

申请日：1999-02-18

Applicant: LAM RES CORP

Inventor： BARONE E ,  GOTTSCHO A ,  VAHEDI VAHID

IPC: C23C14/54 ,  C23C16/52 ,  G06F19/00 ,  H01J37/32

Abstract: A method and apparatus for calibrating a semi-empirical process simulator used to determine process values in a plasma process for creating a desired surface profile on a process substrate includes providing a test model which captures all mechanisms responsible for profile evolution in terms of a set of unknown surface parameters. A set Sets of test conditions processes is are derived for which the profile evolution is governed by only a limited number of parameters. For each set of test conditions process, model test values are selected and a test substrate is substrates are actually subjected to a the test process processes defined by the test values, thereby creating a test surface profile profiles. The test values are used to generate an approximate profile prediction predictions and are adjusted to minimize the discrepancy between the test surface profile profiles and the approximate profile prediction predictions, thereby providing a final model of the profile evolution in terms of the process values.

公开(公告)号：DE69909248T2

公开(公告)日：2004-05-27

申请号：DE69909248

申请日：1999-02-02

Applicant: LAM RES CORP

Inventor： WINNICZEK W ,  VAHEDI VAHID

IPC: H05H1/46 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065

Abstract: A method for reducing erosion of a mask while etching a feature in a first layer underlying the mask is disclosed. The first layer is disposed on a substrate, with the substrate being positioned on a chuck within in a plasma processing chamber. The method includes flowing an etchant source gas into the plasma processing chamber and forming a plasma from the etchant source gas. The method further includes pulsing an RF power source at a predefined pulse frequency to provide pulsed RF power to the chuck. The pulsed RF power has a first frequency and alternates between a high power cycle and a low power cycle at the pulse frequency The pulse frequency is selected to be sufficiently low to cause polymer to be deposited on the mask during the low power cycle.

公开(公告)号：DE69909248D1

公开(公告)日：2003-08-07

申请号：DE69909248

申请日：1999-02-02

Applicant: LAM RES CORP

Inventor： WINNICZEK W ,  VAHEDI VAHID

IPC: H05H1/46 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065

Abstract: A method for reducing erosion of a mask while etching a feature in a first layer underlying the mask is disclosed. The first layer is disposed on a substrate, with the substrate being positioned on a chuck within in a plasma processing chamber. The method includes flowing an etchant source gas into the plasma processing chamber and forming a plasma from the etchant source gas. The method further includes pulsing an RF power source at a predefined pulse frequency to provide pulsed RF power to the chuck. The pulsed RF power has a first frequency and alternates between a high power cycle and a low power cycle at the pulse frequency The pulse frequency is selected to be sufficiently low to cause polymer to be deposited on the mask during the low power cycle.

公开(公告)号：SG10201705049VA

公开(公告)日：2018-01-30

申请号：SG10201705049V

申请日：2017-06-19

Applicant: LAM RES CORP

Inventor： SRIRAMAN SARAVANAPRIYAN ,  WISE RICHARD ,  SINGH HARMEET ,  PATERSON ALEX ,  BAILEY III ANDREW D ,  VAHEDI VAHID ,  GOTTSCHO RICHARD A

Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

公开(公告)号：SG10201401254VA

公开(公告)日：2014-11-27

申请号：SG10201401254V

申请日：2014-04-04

Applicant: LAM RES CORP

Inventor： PATERSON ALEX ,  SINGH HARMEET ,  MARSH RICHARD A ,  LILL THORSTEN ,  VAHEDI VAHID ,  WU YING ,  SRIRAMAN SARAVANAPRIYAN

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

公开(公告)号：MY145493A

公开(公告)日：2012-02-29

申请号：MYPI20053959

申请日：2005-08-23

Applicant: LAM RES CORP

Inventor： PUPPO HELENE DEL ,  LIN FRANK ,  LEE CHRIS ,  VAHEDI VAHID ,  KAMP THOMAS A ,  MILLER ALAN J

IPC: H01L21/302

Abstract: A METHOD FOR ETCHING A POLYSILICON GATE STRUCTURE IN A PLASMA ETCH CHAMBER IS PROVIDED. THE METHOD INITIATES WITH DEFINING A PATTERN PROTECTING A POLYSILICON FILM TO BE ETCHED.THEN, A PLASMA IS GENERATED. NEXT, SUBSTANTIALLY ALL OF THE POLYSILICON FILM THAT IS UNPROTECTED IS ETCHED. THEN, A SILICON CONTAINING GAS IS INTRODUCED AND A REMAINDER OF THE POLYSILICON FILM IS ETCHED WHILE INTRODUCING A SILICON CONTAINING GAS. AN ETCH CHAMBER CONFIGURED TO INTRODUCE A SILICON CONTAINING GAS DURING AN ETCH PROCESS IS ALSO PROVIDED.