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公开(公告)号：WO0031779A9
公开(公告)日：2002-08-29
申请号：PCT/US9927885
申请日：1999-11-24
Applicant: MICROCHIP TECH INC
Inventor： ALEXANDER SAM E , YACH RANDY L , ST AMAND ROGER
IPC: H01L21/768 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/08
CPC classification number: H01L28/40 , H01L27/0805
Abstract: An improved high quality factor capacitive device is implemented on a single, monolithic integrated circuit. The new layout techniques improve the quality factor (Q) of the capacitor by reducing intrinsic resistance of the capacitor by means of reducing the distance between the metal contacts of the top and bottom conductive plates. The layout techniques require laying out the top conductive plate of the capacitor in strips such that metal contacts from the bottom conductive plate pass in between the strips and through the dielectric layer. Alternatively, the apertures may be etched into the top conductive plate so that metal contacts pass through the apertures and connect to the bottom conductive plate.
Abstract translation: 改进的高品质因素电容器件在单个单片集成电路上实现。 新的布局技术通过减小顶部和底部导电板的金属触点之间的距离来降低电容器的固有电阻，从而提高了电容器的品质因数（Q）。 布局技术需要将带状电容器的顶部导电板布置成使得来自底部导电板的金属接触通过条带之间并通过介电层。 或者，孔可以被蚀刻到顶部导电板中，使得金属触点穿过孔并连接到底部导电板。
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公开(公告)号：DE69808020T2
公开(公告)日：2003-05-22
申请号：DE69808020
申请日：1998-10-14
Applicant: MICROCHIP TECH INC
Inventor： DRAKE RODNEY J , TRIECE JOSEPH W , YACH RANDY L , BOLES BRIAN , WOJEWODA IGOR , JOHANSEN DARREL
IPC: G06F9/35
Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
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公开(公告)号：AU2002324924A1
公开(公告)日：2003-04-01
申请号：AU2002324924
申请日：2002-09-09
Applicant: MICROCHIP TECH INC
Inventor： YACH RANDY L , THOMSEN JOSEPH A , BARTLING JAMES R
Abstract: A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines.
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公开(公告)号：AT224558T
公开(公告)日：2002-10-15
申请号：AT98119388
申请日：1998-10-14
Applicant: MICROCHIP TECH INC
Inventor： DRAKE RODNEY J , TRIECE JOSEPH W , YACH RANDY L , BOLES BRIAN , WOJEWODA IGOR , JOHANSEN DARREL
IPC: G06F9/35
Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
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公开(公告)号：WO0237298A2
公开(公告)日：2002-05-10
申请号：PCT/US0146750
申请日：2001-11-05
Applicant: MICROCHIP TECH INC
Inventor： DARMAWASKITA HARTONO , ELLISON RYAN SCOTT , YACH RANDY L , MORENO MIQUEL
CPC classification number: G06J1/00
Abstract: A configurable mixed analog and digital mode controller may be fabricated as a single monolithic device such as an integrated circuit semiconductor die or a multi-chip package (MCP). The configurable mixed analog and digital mode controller may be a microcontroller and/or a digital signal processor (DSP) in combination with both analog and digital peripherals that may be configured and connected together, both before and during operation thereof, to function as a complete controller system.
Abstract translation: 可以将可配置的混合模拟和数字模式控制器制造为诸如集成电路半导体管芯或多芯片封装（MCP）的单个单片器件。 可配置的混合模拟和数字模式控制器可以是微控制器和/或数字信号处理器（DSP）与模拟和数字外围设备的组合，其可以在其操作之前和期间被配置和连接在一起，以用作完整的 控制器系统。
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Patent Agency Ranking
公开(公告)号：DE69808020D1
公开(公告)日：2002-10-24
申请号：DE69808020
申请日：1998-10-14
Applicant: MICROCHIP TECH INC
Inventor： DRAKE RODNEY J , TRIECE JOSEPH W , YACH RANDY L , BOLES BRIAN , WOJEWODA IGOR , JOHANSEN DARREL
IPC: G06F9/35
Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
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公开(公告)号：AT204393T
公开(公告)日：2001-09-15
申请号：AT98119390
申请日：1998-10-14
Applicant: MICROCHIP TECH INC
Inventor： DRAKE RODNEY J , CHIAO JENNIFER , YACH RANDY L , WOJEWODA IGOR , TRIECE JOSEPH W , ALLEN STEVE
Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.
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公开(公告)号：DE112018000744T5
公开(公告)日：2019-10-17
申请号：DE112018000744
申请日：2018-02-07
Applicant: MICROCHIP TECH INC
Inventor： YACH RANDY L , BRAITHWAITE ROHAN
Abstract: Eine Kondensatorstruktur kann eine untere leitende Schicht (z. B. eine Poly-1-Schicht) und eine obere leitende Schicht (z. B. eine darüber liegende Poly-2-Schicht) umfassen, die eine Anode und eine Kathode definieren, und eine dielektrische Schicht (z. B. einen ONO-Schichtstapel) zwischen der oberen leitenden Schicht und der unteren leitenden Schicht aufweisen, wobei sich ein Abschnitt der dielektrischen Schicht (z. B. zumindest die Nitridschicht des ONO-Schichtstapels) über eine Seitenkante der oberen leitenden Schicht hinaus erstreckt. Ein Verfahren, das eine solche Kondensatorstruktur ausbildet, kann ein Distanzstück neben der Seitenkante der oberen leitenden Schicht und über dem ersten Abschnitt der dielektrischen Schicht verwenden, wobei ein Ätzvorgang durchgeführt wird, um einen ersten Abschnitt der dielektrischen Schicht zu entfernen, aber einen zweiten Abschnitt zu schützen, der sich unter dem Distanzstück befindet und sich seitlich über eine Kante der oberen leitenden Schicht hinaus erstreckt.
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公开(公告)号：AU2002307044A1
公开(公告)日：2002-10-21
申请号：AU2002307044
申请日：2002-03-29
Applicant: MICROCHIP TECH INC
Inventor： YACH RANDY L , SCHLANGER STEVEN ERIC
Abstract: A bistable memory device changes logic state each time an event occurs. The bistable memory device has an logic output coupled to a digital processor input. The digital processor reads the logic state of the bistable memory device from its logic output and compares the logic state read to a stored previous logic state obtained from a previous read. If the logic state read and the stored previous logic state are the same, then no event has occurred during the time between the read and previous read of the logic states of the bistable memory device. If different, then an event has occurred during the time between the read and previous read of the logic states of the bistable memory device. The event detection may be used in combination with a digital system communicating by serial digital data transmissions.
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公开(公告)号：DE69801355T2
公开(公告)日：2002-06-13
申请号：DE69801355
申请日：1998-10-14
Applicant: MICROCHIP TECH INC
Inventor： DRAKE J , CHIAO JENNIFER , YACH RANDY L , WOJEWODA IGOR , TRIECE JOSEPH W , ALLEN STEVE
Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.
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