公开(公告)号：DK1066559T3

公开(公告)日：2005-10-03

申请号：DK99911150

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：DE60015969D1

公开(公告)日：2004-12-23

申请号：DE60015969

申请日：2000-04-21

Applicant: QUALCOMM INC

Inventor： BLESSENT LUCA ,  MOTIWALA QUAEED

IPC: H04B1/7093 ,  H04B20060101 ,  H04B1/7113 ,  H04B1/7115 ,  H04B7/005 ,  H04B7/216

Abstract: The punctured pilot channel comprises information symbols of uncertain sign punctured into a sequence of pilot channel symbols of predetermined sign. The apparatus includes an information sign demodulation circuit for determining the sign of the information symbols in response to the pilot channel symbols. A continuous pilot generator generates a non-punctured pilot channel of predetermined sign from the information symbols and the pilot channel symbols. In a first embodiment, the information sign demodulator further comprises a dot product circuit for calculating a dot product of the pilot channel symbols and the punctured information symbols, and a threshold comparator for comparing the dot product to a predetermined threshold.

公开(公告)号：AU2002237908A1

公开(公告)日：2002-07-30

申请号：AU2002237908

申请日：2002-01-17

Applicant: QUALCOMM INC

Inventor： RIDDLE CHRISTOPHER C ,  YEH SHIH-YI ,  FUCHS ROBERT J ,  BLESSENT LUCA ,  MOTIWALA QUAEED

IPC: H04B1/707 ,  H04B1/7117 ,  H04B7/26 ,  H04Q7/38

Abstract: The frame of data is partitioned into a plurality of portions of data symbols. A plurality of channel elements is assigned to demodulate data symbols of correspondingly the plurality of portions of data symbols. The number of the plurality of portions of data symbols is higher in a case at high data rate than a case at low data rate.

公开(公告)号：AU4482500A

公开(公告)日：2000-11-10

申请号：AU4482500

申请日：2000-04-21

Applicant: QUALCOMM INC

Inventor： BLESSENT LUCA ,  MOTIWALA QUAEED

IPC: H04B1/7093 ,  H04B20060101 ,  H04B1/7113 ,  H04B1/7115 ,  H04B7/005 ,  H04B7/216

Abstract: The punctured pilot channel comprises information symbols of uncertain sign punctured into a sequence of pilot channel symbols of predetermined sign. The apparatus includes an information sign demodulation circuit for determining the sign of the information symbols in response to the pilot channel symbols. A continuous pilot generator generates a non-punctured pilot channel of predetermined sign from the information symbols and the pilot channel symbols. In a first embodiment, the information sign demodulator further comprises a dot product circuit for calculating a dot product of the pilot channel symbols and the punctured information symbols, and a threshold comparator for comparing the dot product to a predetermined threshold.

公开(公告)号：CA2324219C

公开(公告)日：2011-05-10

申请号：CA2324219

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A ,  KANG INYUP

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：DE69925720D1

公开(公告)日：2005-07-14

申请号：DE69925720

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH C ,  ZOU QUIZHEN ,  JHA K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI E ,  KANTAK A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：BR0206572A

公开(公告)日：2005-01-18

申请号：BR0206572

申请日：2002-01-17

Applicant: QUALCOMM INC

Inventor： MOTIWALA QUAEED ,  RIDDLE CHRISTOPHER C ,  BLESSENT LUCA ,  YEH SHIH-YI ,  FUCHS ROBERT J

IPC: H04B1/707 ,  H04B1/7117 ,  H04B7/26 ,  H04Q7/38

Abstract: The frame of data is partitioned into a plurality of portions of data symbols. A plurality of channel elements is assigned to demodulate data symbols of correspondingly the plurality of portions of data symbols. The number of the plurality of portions of data symbols is higher in a case at high data rate than a case at low data rate.

公开(公告)号：AT282909T

公开(公告)日：2004-12-15

申请号：AT00926267

申请日：2000-04-21

Applicant: QUALCOMM INC

Inventor： BLESSENT LUCA ,  MOTIWALA QUAEED

IPC: H04B1/7093 ,  H04B20060101 ,  H04B1/7113 ,  H04B1/7115 ,  H04B7/005 ,  H04B7/216

Abstract: The punctured pilot channel comprises information symbols of uncertain sign punctured into a sequence of pilot channel symbols of predetermined sign. The apparatus includes an information sign demodulation circuit for determining the sign of the information symbols in response to the pilot channel symbols. A continuous pilot generator generates a non-punctured pilot channel of predetermined sign from the information symbols and the pilot channel symbols. In a first embodiment, the information sign demodulator further comprises a dot product circuit for calculating a dot product of the pilot channel symbols and the punctured information symbols, and a threshold comparator for comparing the dot product to a predetermined threshold.

公开(公告)号：HK1035594A1

公开(公告)日：2001-11-30

申请号：HK01106221

申请日：2001-09-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：AU2986099A

公开(公告)日：1999-10-11

申请号：AU2986099

申请日：1999-03-04

Applicant: QUALCOMM INC

Inventor： SIH GILBERT C ,  ZOU QUIZHEN ,  JHA SANJAY K ,  KANG INYUP ,  LIN JIAN ,  MOTIWALA QUAEED ,  JOHN DEEPU ,  ZHANG LI ,  ZHANG HAITAO ,  LEE WAY-SHING ,  SAKAMAKI CHARLES E ,  KANTAK PRASHANT A

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0886 ,  G06F15/78

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).