中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.023 seconds)

    11.
    发明专利
    未知

    公开(公告)号：FR2821208B1

    公开(公告)日：2003-04-11

    申请号：FR0102347

    申请日：2001-02-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  FERREIRA PAUL

    IPC: H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H01L21/8239

    Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

    Method for the integration of DRAM memory by providing a cell architecture that augments the density of integration
    13.
    发明专利
    Method for the integration of DRAM memory by providing a cell architecture that augments the density of integration 未知

    公开(公告)号：FR2819633A1

    公开(公告)日：2002-07-19

    申请号：FR0100691

    申请日：2001-01-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  PIAZZA MARC ,  LEVERD FRANCOIS

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: A method for the integration of a Dynamic Random Access Memory (DRAM), allowing a freedom from the alignment margins inherent in the photoengraving of the upper electrode for the contact passage of the bit line, the retreat of the upper electrode being auto-aligned on the lower electrode, consists of: (a) forming a topographical difference at the spot (A) where the opening for the upper electrode is to be realised; (b) depositing a layer of non-doped polysilicon on the upper electrode; (c) producing an implantation of strongly inclined doping in this layer; (d) selectively engraving the non-doped part of the layer situated in the lower part of the zone (A) presenting the topographical difference; (e) and engraving the remaining part of the polysilicon layer as well as the upper electrode layer situated in the lower part.

    SYSTEME DE CONVERSION D'ENERGIE THERMIQUE EN ENERGIE ELECTRIQUE A EFFICACITE AMELIOREE
    14.
    发明专利
    SYSTEME DE CONVERSION D'ENERGIE THERMIQUE EN ENERGIE ELECTRIQUE A EFFICACITE AMELIOREE 未知

    公开(公告)号：FR2982424A1

    公开(公告)日：2013-05-10

    申请号：FR1160209

    申请日：2011-11-09

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： SAVELLI GUILLAUME ,  CORONEL PHILIPPE ,  GAILLARD FREDERIC ,  MONFRAY STEPHANE

    IPC: H01L37/00

    Abstract: Système de conversion d'énergie thermique en énergie électrique (S1) destiné à être disposé entre une source chaude (SC) et une source froide (SF) , comportant des moyens de conversion de l'énergie thermique en énergie mécanique (6) et un matériau piézoélectrique, les moyens de conversion de l'énergie thermique en énergie mécanique (6) comportant des groupes (G1, G2 ) de au moins trois bilames (9, 11, 13) reliés mécaniquement entre eux par leur extrémités longitudinales et suspendus au-dessus d'un substrat (12), chaque bilame (9, 11, 13) comportant deux états stables dans lesquels il présente dans chacun des états une courbure, deux bilames directement adjacentes (9, 11, 13) présentant pour une température donnée des courbures opposées, le passage d'un état à stable des bilames (9, 11, 13) à l'autre provoquant la déformation d'un matériau piézoélectrique.

    18.
    发明专利
    未知

    公开(公告)号：FR2853454B1

    公开(公告)日：2005-07-15

    申请号：FR0304143

    申请日：2003-04-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  MORAND YVES ,  SKOTNICKI THOMAS ,  CERUTTI ROBIN

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

    Abstract: A MOS transistor formed in a silicon substrate (101) comprises: (a) an active zone (100) surrounded by an insulating partition (102); (b) a first conducting strip (103) covering a central strip of the active zone; (c) one or more second conducting strips (105, 106, 107) placed in the active zone plumb with the first strip; (d) some conducting regions (108, 109) placed in two cavities in the insulating partition and joined to the ends of the first and second strips; (e) the surfaces of the silicon opposite the strips and conducting regions are covered with an insulator (130) constituting an oxide grid. An independent claim is also included for the production of this MOS transistor.

    19.
    发明专利
    未知

    公开(公告)号：FR2848724B1

    公开(公告)日：2005-04-15

    申请号：FR0215837

    申请日：2002-12-13

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

    IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

    Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

Patent Agency Ranking