公开(公告)号：DE60316934D1

公开(公告)日：2007-11-29

申请号：DE60316934

申请日：2003-05-02

Applicant: ST MICROELECTRONICS SA

Inventor： CATHELIN ANDREA ,  BERNARD CHRISTOPHE ,  DELPECH PHILIPPE ,  TROADEC PIERRE ,  SALAGER LAURENT ,  GARNIER CHRISTOPHE

IPC: H01L23/52 ,  H01L23/66 ,  H01G17/00 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/822 ,  H01L23/48 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H04Q7/20

Abstract: An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed between the capacitor and the semiconductor component. Preferably, the semiconductor component is placed in proximity to the surface of the substrate and several superposed layers of insulating material cover the surface of the substrate and the semiconductor component. The capacitor is then placed within at least one layer of insulating material above the semiconductor component, and the screen is placed within an intermediate layer of insulating material between the layer incorporating the capacitor and the surface of the substrate.

公开(公告)号：FR2884646B1

公开(公告)日：2007-09-14

申请号：FR0503894

申请日：2005-04-19

Applicant: ST MICROELECTRONICS SA

Inventor： GIRAUDIN JEAN CHRISTOPHE ,  CREMER SEBASTIEN ,  DELPECH PHILIPPE

IPC: H01L21/02 ,  H01G4/33 ,  H01L27/06

Abstract: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.

公开(公告)号：FR2884646A1

公开(公告)日：2006-10-20

申请号：FR0503894

申请日：2005-04-19

Applicant: ST MICROELECTRONICS SA

Inventor： GIRAUDIN JEAN CHRISTOPHE ,  CREMER SEBASTIEN ,  DELPECH PHILIPPE

IPC: H01L21/02 ,  H01G4/33 ,  H01L27/06

Abstract: L'invention porte sur un procédé de fabrication au sein d'un circuit intégré (CI) d'un condensateur ayant au moins deux tranchées capacitives (3a, 3b) s'étendant au sein d'un matériau diélectrique, caractérisé par le fait qu'on réalise une couche métallique (1a) noyée dans ledit matériau diélectrique, on grave le matériau diélectrique avec arrêt sur ladite couche métallique (1a) de façon à former lesdites tranchées (3a, 3b) et on dépose une couche de matériau conducteur formant l'électrode inférieure (4a) du condensateur, au moins sur les flancs desdites tranchées et au contact de ladite couche métallique (1a), ainsi qu'un circuit intégré comprenant un tel condensateur.

公开(公告)号：FR2879815A1

公开(公告)日：2006-06-23

申请号：FR0413415

申请日：2004-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： GIRAUDIN JEAN CHRISTOPHE ,  CREMER SEBASTIEN ,  DELPECH PHILIPPE

IPC: H01L27/06 ,  H01L21/02

Abstract: L'invention propose un procédé de fabrication d'un condensateur dans une couche d'interconnexion, comprenant les étapes suivantes :-dépôt d'une première couche métallique (21);-dépôt d'une première couche d' isolant (31) sur la première couche métallique (21);-dépôt d'une seconde couche métallique (41) sur la première couche d'isolant (31) ;-formation d'une électrode supérieure (4) dans la seconde couche métallique (41);-dépôt d'une seconde couche d'isolant (13) recouvrant l'électrode supérieure (4);-gravure de la seconde couche d'isolant pour former sur cette première couche d'isolant un espaceur (14) entourant l'électrode supérieure (4); puis-formation d'une électrode inférieure (2) et d'un diélectrique (3) par retrait des parties des premières couches métallique et d'isolant non recouvertes par l'électrode supérieure (4) ou l'espaceur (14);-formation d'une ligne d'interconnexion (5).L'invention permet de fabriquer des condensateurs avec un rendement accru, de façon simplifiée à moindre coût et avec un auto-alignement.

公开(公告)号：FR2839581B1

公开(公告)日：2005-07-01

申请号：FR0205712

申请日：2002-05-07

Applicant: ST MICROELECTRONICS SA

Inventor： CATHELIN ANDREA ,  BERNARD CHRISTOPHE ,  DELPECH PHILIPPE ,  TROADEC PIERRE ,  SALAGER LAURENT ,  GARNIER CHRISTOPHE

IPC: H01L23/52 ,  H01G17/00 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/822 ,  H01L23/48 ,  H01L23/522 ,  H01L23/58 ,  H01L23/66 ,  H01L27/04 ,  H04Q7/20

Abstract: An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed between the capacitor and the semiconductor component. Preferably, the semiconductor component is placed in proximity to the surface of the substrate and several superposed layers of insulating material cover the surface of the substrate and the semiconductor component. The capacitor is then placed within at least one layer of insulating material above the semiconductor component, and the screen is placed within an intermediate layer of insulating material between the layer incorporating the capacitor and the surface of the substrate.

公开(公告)号：FR2855323A1

公开(公告)日：2004-11-26

申请号：FR0306031

申请日：2003-05-20

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  REGNIER CHRISTOPHE ,  CREMER SEBASTIEN

IPC: H01L21/02 ,  H01L29/92

公开(公告)号：DE69900484D1

公开(公告)日：2002-01-10

申请号：DE69900484

申请日：1999-05-14

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： DELPECH PHILIPPE ,  REVIL NATHALIE

IPC: G03F1/00 ,  H01L23/525 ,  G03F7/20 ,  H01L21/033

Abstract: The implementation by photolithography of integrated circuit includes at least one fuse (20) comprising pads (3,4) for electrical contacts and a central region (2) substantially in the form of a bar with a thinner region (21) forming a weak point facilitating the breakdown of fuse element by increasing current density in the conditions of standard breakdown. The method comprises the following steps: the formation of an exposition mask reproducing the fuse design (D20) comprising a central region (D2) in the form of a bar, and artificial elements (D22, D23) in the neighbourhood of central region; the formation of etching mask by exposition for the fuse (20) having the central region (2) with the appearance of a thinner region (21) by the optical effect of proximity, so that the width (W2) of thin region is less than the technological minimum (Wmin) determined by the manufacturing method for integrated circuit. Each artificial element (D22, D23) has an edge (D22-1, D23-1) located with respect to the central region (D2) at a distance (DE3), which is less than the technological threshold (SEmin), below which the optical effect of proximity is manifested. The central region (D2) has a width (DW1) chosen so to obtain the width (W1) of fuse (20) substantially equal to the technological minimum (Wmin). The width (W2) of thin region is substantially equal to half the average width (W1) of central region on the outside of thin zone. The optical effect of proximity forms a progressive thinning of central region, and also transitions of thinning with oblique edges. The thinning is by the formation of notches (21-1, 21-2) on the sides of central region. The etching mask has at least one opening greater than the spacing between elements in the fuse design exposition mask. The etching mask is obtained by the deposition of a layer of photosensitive resin onto a layer of integrated circuit, following an exposition step and a step for the resin removal by a solvent. The fuse of integrated circuit is implemented by the etching of a thin layer of polysilicon, metal or alloy, or by etching of a thin layer formed by a pile of metals or alloys. The fuse of integrated circuit is implemented by polysilicon silicide, with a metal as eg. titanium, cobalt, tungsten, tantalum, and the method includes a step of etching in plasma. The implementation of artificial elements (22,23) favours the etching of an oxide layer on the sides of fuse, so that the fuse has oxide spacers which do not cover entirely the sides of thin zone.

公开(公告)号：FR2801426A1

公开(公告)日：2001-05-25

申请号：FR9914486

申请日：1999-11-18

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  ARNAL VINCENT ,  LIS SANDRA

IPC: H01L21/02 ,  H01L21/314 ,  H01L29/92 ,  H01G4/08 ,  H01G4/33

Abstract: Capacitive structure (20) on a Si substrate (10) comprises first (1) and second (3) electrode layers and dielectric layer (2) comprising a homogeneous combination of molecules of at least two dielectrics with permittivities ( iota ) behaving oppositely as a function of electric field. The proportion of each dielectric is empirically chosen so that capacitance varies as little as possible with voltage. The dielectric of the dielectric layer (2) has formula SiOxNy, where x is different from y. The material of the first (1) and second (2) electrode layers is selected from aluminum, copper, tungsten, titanium, titanium nitride and their alloys. Independent claims are given for: (a) a dielectric comprising a homogeneous combination of molecules of at least two dielectrics with permittivities ( iota ) behaving oppositely as a function of electric field, and where the proportion of each dielectric in the combination is empirically chosen such that the combination has a permittivity whose variation as a function of electric field is as low as possible; and (b) a method of production of the above capacitive structure.

公开(公告)号：FR2911006A1

公开(公告)日：2008-07-04

申请号：FR0700026

申请日：2007-01-03

Applicant: ST MICROELECTRONICS SA

Inventor： GIRAUDIN JEAN CHRISTOPHE ,  DELPECH PHILIPPE ,  SEILLER JACKY

IPC: H01L27/02 ,  H01L21/02 ,  H01L21/60 ,  H01L23/52

Abstract: Une puce de circuit électronique intégré ccmprend une inductance (1) qui est disposée par dessus une couche (106) de protection de niveaux de métallisation de la puce (102-105). L'inductance peut alors être épaisse, selon une direction (N) perpendiculaire à une surface d'un substrat de la puce (100). L'inductance présente alors une résistance électrique réduite et peut avoir un coefficient de qualité élevé. En outre, une inductance selon l'invention peut être réalisée en même temps que des plots de connexion de la puce (19) à un support de puce selon la technologie « flip-chip ».

公开(公告)号：DE602004002986D1

公开(公告)日：2006-12-14

申请号：DE602004002986

申请日：2004-05-12

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  REGNIER CHRISTOPHE ,  CREMER SEBASTIEN

IPC: H01L21/02 ,  H01L29/92