公开(公告)号：DE60041056D1

公开(公告)日：2009-01-22

申请号：DE60041056

申请日：2000-08-16

Applicant: ST MICROELECTRONICS SRL

Inventor： GERACI ANTONINO ,  LISI CARLO ,  BEDARIDA LORENZO ,  SFORZIN MARCO

IPC: G11C16/28 ,  G11C7/12

Abstract: A direct-comparison reading circuit for a nonvolatile memory array (2) having a plurality of memory cells (4) arranged in rows and columns (9), and at least one bit line (7), includes at least one array line (13), selectively connectable to the bit line (7), and a reference line (14); a precharging circuit (17) for precharging the array line (13) and reference line (14) at a preset precharging potential (VPC); at least one comparator (35) having a first terminal connected to the array line (13), and a second terminal connected to the reference line (14); and an equalization circuit (15, 23, 26) for equalizing the potentials of the array line (13) and reference line (14) in the precharging step. In addition, the reading circuit includes an equalization line (15) distinct from the reference line (14); and controlled switches (23, 26) for connecting, in the precharging step, the equalization line (15) to the array line (13) and to the reference line (14), and for disconnecting the equalization line (15) from the array line (13) and from the reference line (14) at the end of the precharging step.

公开(公告)号：DE69933203D1

公开(公告)日：2006-10-26

申请号：DE69933203

申请日：1999-07-21

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  DISEGNI FABIO ,  DIMA VINCENZO ,  BARTOLI SIMONE

IPC: H03K17/06 ,  H03K17/30 ,  H03K19/00

Abstract: The present invention refers to a circuit disposal of a transistor shaped like a diode, in particular to a disposal able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. In an embodiment the circuit disposal comprises a first pMOS transistor (300) having a second pMOS transistor (301) shaped like a diode connected between the gate and the drain of the first transistor and a current generator (310) connected to the gates of the two transistors. Such a circuitry disposal it is also applicable to a nMOS transistor. From a general point of view this invention refers to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series to the gate that provides an opportune delta of voltage.

公开(公告)号：IT1314090B1

公开(公告)日：2002-12-04

申请号：ITMI992487

申请日：1999-11-26

Applicant: ST MICROELECTRONICS SRL

Inventor： DIMA VINCENZO ,  BEDARIDA LORENZO ,  BETTINI LUIGI

IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.

公开(公告)号：ITTO20010530A1

公开(公告)日：2002-12-02

申请号：ITTO20010530

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI EMANUELE ,  GERACI ANTONIO ,  SFORZIN MARCO ,  BEDARIDA LORENZO

IPC: G11C7/10

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

公开(公告)号：ITMI992487A1

公开(公告)日：2001-05-28

申请号：ITMI992487

申请日：1999-11-26

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  BETTINI LUIGI

IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.

公开(公告)号：ITMI20001315D0

公开(公告)日：2000-06-13

申请号：ITMI20001315

申请日：2000-06-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  GERACI ANTONINO ,  LISI CARLO ,  DIMA VINCENZO

IPC: G11C16/28

Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

公开(公告)号：IT1319130B1

公开(公告)日：2003-09-23

申请号：ITMI20002529

申请日：2000-11-23

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  VANDI LUCA ,  LISI CARLO ,  BELLINI ANDREA

IPC: G05F3/24

公开(公告)号：DE69520665T2

公开(公告)日：2001-08-30

申请号：DE69520665

申请日：1995-05-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  BEDARIDA LORENZO ,  FUSILLO GIUSEPPE ,  SILVAGNI ANDREA

IPC: G11C17/00 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00 ,  G11C7/00

公开(公告)号：ITMI992576A1

公开(公告)日：2001-06-13

申请号：ITMI992576

申请日：1999-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  DIMA VINCENZO ,  GERACI ANTONINO

IPC: G05F3/24

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

公开(公告)号：ITTO20010530D0

公开(公告)日：2001-06-01

申请号：ITTO20010530

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI EMANUELE ,  GERACI ANTONIO ,  SFORZIN MARCO ,  BEDARIDA LORENZO

IPC: G11C7/10

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.