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    11.
    发明专利
    未知

    公开(公告)号：IT1318892B1

    公开(公告)日：2003-09-19

    申请号：ITMI20002018

    申请日：2000-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MANSTRETTA ALESSANDRO ,  TORELLI GUIDO

    IPC: G11C7/06 ,  G11C16/28

    Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.

    13.
    发明专利
    未知

    公开(公告)号：ITMI20002018A1

    公开(公告)日：2002-03-15

    申请号：ITMI20002018

    申请日：2000-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  TORELLI GUIDO ,  MANSTRETTA ALESSANDRO

    IPC: G11C7/06 ,  G11C16/28

    Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.

    14.
    发明专利
    未知

    公开(公告)号：ITTO20000892D0

    公开(公告)日：2000-09-22

    申请号：ITTO20000892

    申请日：2000-09-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO

    IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

    Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

    15.
    发明专利
    未知

    公开(公告)号：ITMI20001585D0

    公开(公告)日：2000-07-13

    申请号：ITMI20001585

    申请日：2000-07-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO ,  PIERIN ANDREA ,  GREGORI STEFANO ,  SANGALLI MIRIAM

    IPC: G11C16/08

    Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.

    16.
    发明专利
    未知

    公开(公告)号：ITTO990993D0

    公开(公告)日：1999-11-16

    申请号：ITTO990993

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

    IPC: G11C11/56 ,  G11C16/30

    Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

    19.
    发明专利
    未知

    公开(公告)号：IT1316002B1

    公开(公告)日：2003-03-26

    申请号：ITRM20000577

    申请日：2000-11-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MOTTA ILARIA ,  MICHELONI RINO ,  TORELLI GUIDO

    IPC: G05F1/56

    Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

    20.
    发明专利
    未知

    公开(公告)号：ITTO20000892A1

    公开(公告)日：2002-03-22

    申请号：ITTO20000892

    申请日：2000-09-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO ,  MICHELONI RINO

    IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

    Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

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