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    11.
    发明专利
    未知

    公开(公告)号：DE69534919T2

    公开(公告)日：2007-01-25

    申请号：DE69534919

    申请日：1995-10-30

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

    IPC: H01L29/06 ,  H01L29/74 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

    Abstract: A MOS technology power device comprises: a semiconductor material layer (2) of a first conductivity type; a conductive insulated gate layer (7,8,9) covering the semiconductor material layer (2); a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of an elongated body stripe, each elementary functional unit further comprising an elongated window (12) in the insulated gate layer (7,8,9) extending above the elongated body stripe (3). Each body stripe (3) includes at least one source portion (60;61;62) doped with dopants of the first conductivity type, intercalated with a body portion (40;41;3') of the body stripe (3) wherein no dopant of the first conductivity type are provided. The conductive insulated gate layer (7,8,9) comprises a first insulating material layer (7) placed above the semiconductor material layer (2), a conductive material layer (8) placed above the first insulating material layer (7), and a second insulating material layer (9) placed above the conductive material layer (8). Insulating material sidewall spacers (13) are provided to seal edges of the elongated window (12) in the insulated gate layer (7,8,9).

    15.
    发明专利
    未知

    公开(公告)号：DE602004011195D1

    公开(公告)日：2008-02-21

    申请号：DE602004011195

    申请日：2004-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FERRARA MAURIZIO MARIA ,  MAGRI ANGELO ,  MINOTTI AGATINO

    IPC: H01L23/31 ,  H01L23/495 ,  H01L23/52

    Abstract: A vertical conduction power electronic device package (1) and corresponding assembly method comprising at least a metal frame (2) suitable to house at least a plate or first semiconductor die (16,35) having at least a first (17) and a second conduction terminal (18) on respective opposed sides of the first die (16,35). The first conduction terminal (17) being in contact with said metal frame (2) and comprising at least an intermediate frame (23,24) arranged in contact with said second conduction terminal (18).

    16.
    发明专利
    未知

    公开(公告)号：DE69533134T2

    公开(公告)日：2005-07-07

    申请号：DE69533134

    申请日：1995-10-30

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a plurality of elementary functional units which contribute for respective fractions to an overall current of the power device and which are formed in a semiconductor material layer (2) of a first conductivity type. Each elementary functional unit comprises a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of a body stripe (3) elongated in a longitudinal direction on a surface of the semiconductor material layer (2). Each body stripe (3) includes at least one source portion (60) doped with dopants of the first conductivity type which is intercalated with a body portion (40) of the body stripe (3) wherein no dopants of the first conductivity type are provided.

    18.
    发明专利
    未知

    公开(公告)号：DE69631524D1

    公开(公告)日：2004-03-18

    申请号：DE69631524

    申请日：1996-07-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGRI ANGELO ,  ZAMBRANO RAFFAELE ,  FRISINA FERRUCCIO

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

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