公开(公告)号：DE69710593D1

公开(公告)日：2002-03-28

申请号：DE69710593

申请日：1997-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： PORTALURI SALVATORE ,  PISATI VALERIO

IPC: G05B19/00 ,  H03H11/04 ,  H03F1/00

Abstract: A feedforward structure with programmable zeros for synthesizing continuous-time filters, delay lines and the like, whose particularity is that it comprises a first cell and a second cell which are cascade-connected, each one of the first and second cells comprising a first pair (1, 2) of bipolar transistors in which the emitter terminals are connected to a current source (5), the first pair of transistors being connected to a second pair of transistors (6, 7), a current source (11) being connected to the emitter terminals of the second pair of transistors, a first high-impedance element (C) being connected between the first and second pairs of transistors, a second high-impedance element (C) being connected in output to the second pair of transistors, a fifth transistor (8) being connected between the collector terminal of a first transistor (1) of the first pair of transistors and a collector terminal of a second transistor (2) of the second pair of transistors, the base terminal of the fifth transistor (8) receiving a signal which is taken from the collector terminal of the first transistor of the first pair of transistors and is taken with a positive sign in the first cell and with a negative sign in the second cell, in order to determine a transfer function with a pair of singularities at the numerator, the second transistors (2, 7) of the first and second pairs being controlled respectively by current sources (4, 9) which have mutually different values.

公开(公告)号：ITMI20000393A1

公开(公告)日：2001-08-29

申请号：ITMI20000393

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTELLO RINALDO ,  PORTALURI SALVATORE ,  PISATI VALERIO ,  CAZZANIGA MARCO

IPC: H03F1/42 ,  H03H11/04

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

公开(公告)号：DE69426776T2

公开(公告)日：2001-06-13

申请号：DE69426776

申请日：1994-12-27

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PORTALURI SALVATORE

IPC: G06G7/16 ,  G06G7/163

Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.

公开(公告)号：DE69323483T2

公开(公告)日：1999-06-24

申请号：DE69323483

申请日：1993-04-06

Applicant: ST MICROELECTRONICS SRL

Inventor： BETTI GIORGIO ,  MOLONEY DAVID ,  PORTALURI SALVATORE

IPC: H03F3/68 ,  H03G1/00 ,  H03G1/04 ,  H03G3/20 ,  H03G3/30 ,  H03G5/16

Abstract: A variable gain amplifier is composed of a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.

公开(公告)号：DE69825250D1

公开(公告)日：2004-09-02

申请号：DE69825250

申请日：1998-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： DE MICHELI MARCO ,  PORTALURI SALVATORE ,  BOLLATI GIACOMINO ,  BRUCCOLERI MELCHIORRE

IPC: G05F3/26 ,  H03F3/30 ,  H03H11/04

Abstract: A transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor (4) across which a constant voltage is input; the transconductor is connected to a DAC (7) to set a reference current (IR); a feedback loop (9, 10, 23, 11) is provided between the output of the transconductor (4) and its input; the particularity of the circuit is the fact that it further comprises means (20, 22, 24) for mirroring the reference current (IR) set by the DAC (7) which are suitable to mirror the current both to the feedback loop and to at least one cell of a filter which is cascade-connected.

公开(公告)号：DE69901781D1

公开(公告)日：2002-07-18

申请号：DE69901781

申请日：1999-03-05

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  SAVO ALESSANDRO ,  MARCHESE STEFANO

IPC: H03G1/00

Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations, comprising a differential input stage which is biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors, characterized in that it comprises two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.

公开(公告)号：ITMI20000393D0

公开(公告)日：2000-02-29

申请号：ITMI20000393

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTELLO RINALDO ,  PORTALURI SALVATORE ,  PISATI VALERIO ,  CAZZANIGA MARCO

IPC: H03F1/42 ,  H03H11/04

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

公开(公告)号：DE69325888T2

公开(公告)日：2000-01-20

申请号：DE69325888

申请日：1993-02-26

Applicant: ST MICROELECTRONICS SRL

Inventor： ALINI ROBERTO ,  MOLONEY DAVID ,  GORNATI SILVANO ,  PORTALURI SALVATORE

IPC: G06F13/38 ,  G11C5/00

公开(公告)号：DE69925593D1

公开(公告)日：2005-07-07

申请号：DE69925593

申请日：1999-09-08

Applicant: ST MICROELECTRONICS SRL

Inventor： GARBELLI LUIGI EUGENIO ,  LUCIANO GUISEPPE ,  PORTALURI SALVATORE

IPC: G01R31/40 ,  G05F1/46

Abstract: The monitoring of multiple supply voltages of an IC, part of which are externally provided and part of which, of different voltage and sign, are internally generated (12V, 5V, 3.3V, 2.5V, -5V), consisting in generating a logic signal (NPOR) monitoring the correctness of all said supply voltages after an initial soft start phase of the turn-on process, is done by using a single external capacitor (C) connected to a pin of the integrated circuit.

公开(公告)号：DE69825558D1

公开(公告)日：2004-09-16

申请号：DE69825558

申请日：1998-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PORTALURI SALVATORE ,  PISATI VALERIO ,  ZANGRANDI LUIGI

IPC: H03K7/08

Abstract: A device for generating pulses of high-precision programmable duration, whose particularity is the fact that it comprises: -- first pulse generator means (1) which are suitable to receive in input a pulse generation command signal (IN) and to emit in output a first pulse for loading the contents of a register in counter means (2); -- second pulse generator means (4), triggered by the first pulse in output from the first pulse generator means (1); -- third pulse generator means (6), triggered by a second pulse emitted by the second pulse generator means and suitable to generate a third pulse to restart the second pulse generator means; the second pulse emitted by the second pulse generator means (4) constituting a clock signal for the counter means (2) in order to produce a decrement in the counter means; the signal in output from the counter means (2) being the pulsed signal to be generated (OUT); the duration of the pulsed signal being determined by the content of the counter means (2).