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公开(公告)号：DE69128987T2
公开(公告)日：1998-06-18
申请号：DE69128987
申请日：1991-06-17
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).
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公开(公告)号：IT1246467B
公开(公告)日：1994-11-19
申请号：IT2181690
申请日：1990-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.
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公开(公告)号：DE69427471T2
公开(公告)日：2002-04-25
申请号：DE69427471
申请日：1994-07-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ALINI ROBERTO , CASTELLO RINALDO , VAI GIANFRANCO
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公开(公告)号：DE69427471D1
公开(公告)日：2001-07-19
申请号：DE69427471
申请日：1994-07-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ALINI ROBERTO , CASTELLO RINALDO , VAI GIANFRANCO
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公开(公告)号：DE69128987D1
公开(公告)日：1998-04-09
申请号：DE69128987
申请日：1991-06-17
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).
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Patent Agency Ranking
公开(公告)号：DE69031863D1
公开(公告)日：1998-02-05
申请号：DE69031863
申请日：1990-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/0233 , H03K3/2897 , H03K3/023
Abstract: An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).
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公开(公告)号：DE69031863T2
公开(公告)日：1998-04-16
申请号：DE69031863
申请日：1990-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/0233 , H03K3/2897 , H03K3/023
Abstract: An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).
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公开(公告)号：IT1250908B
公开(公告)日：1995-04-21
申请号：IT2072890
申请日：1990-06-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948 , H01L
Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).
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公开(公告)号：DE69519663D1
公开(公告)日：2001-01-25
申请号：DE69519663
申请日：1995-03-07
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , VAI GIANFRANCO , PORTALURI SALVATORE , DEMICHELI MARCO
Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.
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公开(公告)号：IT9021816D0
公开(公告)日：1990-10-22
申请号：IT2181690
申请日：1990-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.
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