中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.022 seconds)

    Non-volatile memory with the functional capability of simultaneous modification of the contents and burst mode read or page mode read
    11.
    发明公开
    Non-volatile memory with the functional capability of simultaneous modification of the contents and burst mode read or page mode read 审中-公开
    与内容改变的功能能力的非易失性存储器，并且同时突发或页面模式读取

    公开(公告)号：EP1073064A1

    公开(公告)日：2001-01-31

    申请号：EP99830495.0

    申请日：1999-07-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bedarida, Lorenzo ,  Geraci, Antonino ,  Sali, Mauro ,  Bartoli, Simone

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/10 ,  G11C16/26

    Abstract: An electrically alterable semiconductor memory comprises at least two substantially independent memory banks (1A, 1B), and first control circuit means (2, 4A, 4B) for controlling operations of electrical alteration of the content of the memory, capable of permitting the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit means (6, 4A, 4B) capable of permitting, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode read or page mode read operation or a standard read operation for reading the content of the other memory bank.

    Abstract translation: 电可变半导体存储器包括至少两个实质独立的存储体（1A，1B），以及第一控制电路装置（2，图4A，图4B），用于控制所述存储器的内容的电改变的操作，能够允许选择性执行的 的操作的至少两个存储体中的一个的内容的电改变的。 因此，该存储器包括第二控制电路装置（6，4A，4B），其能够允许的，同时，随着所述操作的至少两个存储体中的一个的内容的电改变的，突发模式读或页面模式下读手术或 标准读取操作用于读取其它存储体的内容。

    Sectored semiconductor memory device with configurable memory sector addresses
    12.
    发明公开
    Sectored semiconductor memory device with configurable memory sector addresses 失效
    Sektorbasierter Halbleiterspeicher mit verstellbaren Sektoradressen

    公开(公告)号：EP0905704A1

    公开(公告)日：1999-03-31

    申请号：EP97830467.3

    申请日：1997-09-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bartoli, Simone ,  Dima, Vincenzo ,  Sali, Mauro Luigi

    IPC: G11C8/00 ,  G11C16/06

    CPC classification number: G11C8/12 ,  G11C16/08

    Abstract: A memory device comprises a plurality of independent memory sectors, external address signal inputs (2) for receiving external address signals (A0-A17) for addressing individual memory locations of the memory device, the external address signals (A0-A17) comprising external memory sector address signals (A12-A17) allowing for individually addressing each memory sector, and a memory sector selection means (11) for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals (A12-A17). A first and a second alternative internal memory sector address signal paths (6,7) are provided for supplying the external memory sector address signals (A12-A17) to the memory sector selection means (11), the first path (6) providing no logic inversion and the second path (7) providing logic inversion. Programmable means (12) allows for activating either one or the other of the first and second internal memory sector address signal paths (6,7), so that a position of each memory sector in a space of values (00000h - 3FFFFh) of the external address signals (A0-A17) can be changed by activating either one or the other of the first and second internal memory sector address signal paths (6,7).

    Abstract translation: 存储器件包括多个独立的存储器扇区，用于接收用于寻址存储器件的各个存储器位置的外部地址信号（A0-A17）的外部地址信号输入（2），包括外部存储器的外部地址信号（A0-A17） 允许单独寻址每个存储器扇区的扇区地址信号（A12-A17）和用于根据外部存储器扇区地址信号（A12-A17）的值来选择多个存储器扇区之一的存储器扇区选择装置（11） 。 提供第一和第二替代的内部存储器扇区地址信号路径（6,7），用于将外部存储器扇区地址信号（A12-A17）提供给存储器扇区选择装置（11），第一路径（6）不提供 逻辑反演和第二路径（7）提供逻辑反演。 可编程装置（12）允许激活第一和第二内部存储器扇区地址信号路径（6,7）中的一个或另一个，使得每个存储器扇区在空间中的位置（00000h-3FFFFh） 可以通过激活第一和第二内部存储器扇区地址信号路径（6,7）中的一个或另一个来改变外部地址信号（A0-A17）。

    Autotesting method of a memory cells matrix, particularly of the non-volatile type
    16.
    发明公开
    Autotesting method of a memory cells matrix, particularly of the non-volatile type 审中-公开
    Verfahren zum Selbstest einer Speichermatrix，insbesondere einesnichtflüchtigenSpeichers

    公开(公告)号：EP1324348A1

    公开(公告)日：2003-07-02

    申请号：EP01830832.0

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Geraci, Antonino ,  Campisi, Alberto ,  Bedarida, Lorenzo ,  Bartoli, Simone

    IPC: G11C29/00

    CPC classification number: G11C29/44

    Abstract: An autotesting method of a cells matrix of a memory device is disclosed which comprises the steps of:

    reading the values contained in a plurality of the memory cells;
    comparing the read values with reference values;
    signalling mismatch of the read values with the reference values as an error situation; and
    storing the error situations.

    In the autotesting method, the reading, comparing, signalling, and storing steps are repeated for all the memory cells in an matrix column.
    The autotesting method according to the invention further comprises the steps of:

    storing the addresses of any columns having at least one error situation; and
    repeating all the preceding steps according to a step of scanning all the matrix columns.

    Advantageously according to the invention, all said steps are internally realized in the memory device.
    Also disclosed is a memory device with a autotesting architecture, which device is adapted to implement the autotesting method according to the invention.

    Abstract translation: 公开了一种存储器件的单元矩阵的自动测试方法，其包括以下步骤：读取多个存储器单元中包含的值; 将读取的值与参考值进行比较; 将读取值与参考值的信令不匹配作为错误情况; 并存储错误情况。 在自动测试方法中，对矩阵列中的所有存储单元重复读取，比较，信令和存储步骤。 根据本发明的自动测试方法还包括以下步骤：存储具有至少一个错误情况的任何列的地址; 并且根据扫描所有矩阵列的步骤重复所有前述步骤。 有利地，根据本发明，所有所述步骤在内部实现在存储器件中。 还公开了具有自动测试架构的存储器件，该器件适于实现根据本发明的自动测试方法。

    Non-volatile memory device with burst mode reading and corresponding reading method
    20.
    发明公开
    Non-volatile memory device with burst mode reading and corresponding reading method 有权
    NichtflüchtigerSpeicher mit Burstlesebetrieb sowie entsprechendes Leseverfahren

    公开(公告)号：EP1103978A1

    公开(公告)日：2001-05-30

    申请号：EP99830723.5

    申请日：1999-11-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bartoli, Simone ,  Geraci, Antonino ,  Sali, Mauro ,  Bedarida, Lorenzo

    IPC: G11C7/00

    CPC classification number: G11C7/1072 ,  G11C7/1033 ,  G11C7/1045

    Abstract: The invention relates to a read control circuit portion (1) and an attendant reading method for an electronic memory device (2) integrated in a semiconductor and including a non-volatile memory matrix (4) with associated row and column decoders (5,6) connected to respective outputs of an address counter (7), an ATD circuit (12) for detecting an input transaction as the memory device is being accessed, and read amplifiers (8) and attendant registers (10) for transferring the data read from the memory (2) to the output. The control circuit portion (1) comprises a detection circuit block (15) which is input a clock signal (CK) and a logic signal (BAN) to enable reading in the burst mode, and a burst read mode control logic (3) connected downstream of the circuit block (15).
    The method of this invention comprises accessing the memory matrix in a random read mode; detecting a request for access in the burst read mode; and executing the parallel reading of a plurality of memory words during a single period of time clocked by a clock signal (CK).

    Abstract translation: 本发明涉及集成在半导体中并且包括具有相关行和列解码器（5,6）的非易失性存储器矩阵（4）的电子存储器件（2）的读控制电路部分（1）和辅助读取方法 ），连接到地址计数器（7）的各个输出的ATD电路（12），用于检测作为存储器件被访问的输入事务的ATD电路（12），以及读取放大器（8）和从站寄存器（10） 存储器（2）输出。 控制电路部分（1）包括检测电路块（15），其输入时钟信号（CK）和逻辑信号（BAN）以使能在突发模式下进行读取，并且连接脉冲串读取模式控制逻辑（3） 在电路块（15）的下游。 本发明的方法包括以随机读取模式访问存储矩阵; 在突发读取模式下检测访问请求; 以及在由时钟信号（CK）计时的单个时间段内执行多个存储字的并行读取。

Patent Agency Ranking