公开(公告)号：EP0451883B1

公开(公告)日：2002-12-18

申请号：EP91200496.7

申请日：1991-03-07

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Vajana, Bruno ,  Lucherini, Silvia

IPC: H01L27/112 ,  H01L21/8246

CPC classification number: H01L27/11253 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11266

公开(公告)号：EP1178491A1

公开(公告)日：2002-02-06

申请号：EP00830553.4

申请日：2000-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Gastaldi, Roberto ,  Cappelletti, Paolo ,  Casagrande, Giulio ,  Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory, particularly of the electrically programmable and erasable type such as a flash memory, comprises at least one two-dimensional array (SCT) of memory cells (MC) with a plurality of rows (row0-row511) and a plurality of columns (COL) of memory cells. The columns of the two-dimensional array are grouped in a plurality of packets (CP0-CP1), and the memory cells belonging to the columns of each packet are formed in a respective semiconductor region (4) with a first type of conductivity, this region (4) being distinct from the semiconductor regions (4) with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. It is thus possible to produce memory units of very small dimensions (for example, bytes, words, or long words) which can be erased individually, without excessive overhead in terms of area.

Abstract translation: 半导体存储器，特别是诸如闪存的电可编程和可擦除类型的半导体存储器包括至少一个具有多个行（行0-行511）和多个列的存储器单元（MC）的二维阵列（SCT） （COL）的存储单元。 二维阵列的列被分组为多个分组（CP0-CP1），并且属于每个分组的列的存储器单元以第一类型的导电率形成在相应的半导体区域（4）中，这 区域（4）与半导体区域（4）不同，其中形成属于剩余包的列的存储器单元的第一导电类型。 具有第一导电类型的半导体区域将属于每行的存储器单元组划分为构成可以单独修改的基本存储器单元的多个存储器单元子集。 因此可以产生非常小尺寸的存储单元（例如，字节，单词或长单词），其可以单独擦除，而没有面积方面的过度开销。

公开(公告)号：EP1096575A1

公开(公告)日：2001-05-02

申请号：EP99830629.4

申请日：1999-10-07

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The memory cell (101) is of the type with a single level of polysilicon, and is produced in a substrate (102) of semiconductor material with a first type of conductivity, and comprises a control gate region (6) with a second type of conductivity, formed in the substrate (102) in a first region of active area (30); regions of source (4a, 4b) and drain (5a, 5b) with the second type of conductivity, formed in the substrate (102) in a second region of active area (31); and a floating gate region (9) which extends transversely relative to the first (30) and the second (31) regions of active area. The control gate region (6) is surrounded by a first well (103) with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well (108) with the second type of conductivity. The regions of source (4a, 4b) and drain (5a, 5b) are accommodated in a second well (104) with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well (112) with the second type of conductivity.

Abstract translation: 存储单元（101）是具有单层多晶硅的类型，并且在具有第一类导电性的半导体材料的衬底（102）中制造，并且包括具有第二类型的多晶硅的控制栅极区域（6） 导电性，形成在有源区域（30）的第一区域中的衬底（102）中; 源极（4a，4b）和具有第二类型导电性的漏极（5a，5b）的区域在有源区域（31）的第二区域中形成在衬底（102）中。 以及相对于有效区域的第一（30）和第二（31）区域横向延伸的浮动栅极区域（9）。 控制栅极区域（6）由具有第一类型导电性的第一阱（103）包围，第一阱具有第二类型的导电性，第三阱又由具有第二类型导电性的第三阱（108）包围。 源极（4a，4b）和漏极（5a，5b）的区域被容纳在具有第一类型导电性的第二阱（104）中，第二阱导电性又被第四阱（112）包围并在第二阱 导电类型。

公开(公告)号：EP2015357A1

公开(公告)日：2009-01-14

申请号：EP07425423.6

申请日：2007-07-09

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Benvenuti, Augusto ,  Cappelletti, Paolo ,  Bez, Roberto ,  Pirovano, Agostino

IPC: H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

Abstract: A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).

Abstract translation: 于一体的制造单元的阵列的方法（1）的半导体材料的worin的第一导电类型的公共导电区（11）和一个第二导电类型的共享控制区域（12）的复数，在形成 身体。 共享控制区（12）上的公共导电区（11）延伸，并且尾盘反弹通过绝缘区域（32）分隔。 然后，网格状层（36）形成在所述主体（1）来分隔空区域的第一多个（38）直接覆盖所述主体和半导体材料的导电区域和第一导电类型（44）由形成 填充空区域（38），每个导电区域上形成的第一多个，与普通传导区在一起并且连接到自己的共享控制区域（12），双极结型晶体管（20）。

公开(公告)号：EP0926687B1

公开(公告)日：2005-03-02

申请号：EP97830693.4

申请日：1997-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Olivo, Marco

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/106 ,  G11C29/52 ,  G11C29/76

Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

公开(公告)号：EP1067557B1

公开(公告)日：2005-02-02

申请号：EP99830390.3

申请日：1999-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo

IPC: G11C11/00 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C11/005 ,  G11C16/34

公开(公告)号：EP0704851B1

公开(公告)日：2001-11-28

申请号：EP94830459.7

申请日：1994-09-27

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Casagrande, Giulio

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  H01L27/115

CPC classification number: H01L27/115 ,  G11C16/0416 ,  G11C16/16

公开(公告)号：EP1067557A1

公开(公告)日：2001-01-10

申请号：EP99830390.3

申请日：1999-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo

IPC: G11C11/00 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C11/005 ,  G11C16/34

Abstract: A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout, both are divided into blocks of cells formed in substrate regions isolated from one another. In said second matrix, the information is organized in pages each one contained in a row of memory cells of one of said block of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of polarity opposite to the single supply voltage of the device is applied during an erasing phase to a single wordline selected by means of said row decoder, to page-erase said information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block.
A logical circuit confirms the programmed state of each cell containing a logic zero information of the not erased rows of the block after one or more rows or pages have been erased, applying said first boosted voltage to a wordline at a time and said supply voltage to one or more bitlines at a time for confirming a preexistent programmed state, while keeping to ground voltage the common source of all the cells of the block and the confined isolated region of the substrate.

Abstract translation: 闪存兼容的EEPROM器件具有第一闪存矩阵和具有基本相似布局的EEPROM功能的第二矩阵，它们都被分成在彼此隔离的衬底区域中形成的单元的块。 在所述第二矩阵中，所述信息被组织成每一个包含在所述矩阵的所述细分块之一的一行存储器单元中的页面。 包括行解码器的分级结构寻址块的所选行的所有单元的字线，在选择行中的单个单元时与列解码器协作。 在擦除阶段期间，将与器件的单个电源电压相反的极性提升的电压施加到通过所述行解码器选择的单个字线中，以通过将升压电压施加到所有所述的公共源的页面擦除所述信息 嵌段的单元和包含嵌段的所有单元的基材的分离区。 一个逻辑电路确认每一个单元的编程状态，该单元包含一个或多个行或页被擦除之后的块的未擦除的行的逻辑零信息，一次将所述第一升压电压施加到字线，并将所述电源电压提供给 一个或多个位线一次用于确认预先设定的状态，同时保持接地电压为块的所有单元的共同源和衬底的有限隔离区。