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    A non-volatile memory device supporting high-parallelism test at wafer level
    13.
    发明公开
    A non-volatile memory device supporting high-parallelism test at wafer level 有权
    EinnichtflüchtigerSpeicher mitUnterstützungvon hochparallelem Test auf Waferebene

    公开(公告)号：EP1672647A1

    公开(公告)日：2006-06-21

    申请号：EP04106609.3

    申请日：2004-12-15

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Lomazzi, Guido ,  Renna, Ilaria ,  Maccarrone, Marco

    IPC: G11C29/00

    CPC classification number: G11C29/1201 ,  G11C16/04 ,  G11C29/006 ,  G11C29/16 ,  G11C29/46 ,  G11C2029/2602

    Abstract: A non-volatile memory device (100) is proposed. The non-volatile memory device includes a chip (105) of semiconductor material. The chip includes a memory (202) and control means (204,210,214) for performing a programming operation (314), an erasing operation (312) and a reading operation (316) on the memory in response to corresponding external commands. The chip further includes testing means (118, 120, 220, 225, 230) for performing at least one test process including the repetition of at least one of said operations by the control means, and a single access element (118) for enabling the testing means.

    Abstract translation: 提出了一种非易失性存储器件（100）。 非易失性存储器件包括半导体材料的芯片（105）。 芯片包括用于响应于相应的外部命令在存储器上执行编程操作（314），擦除操作（312）和读取操作（316）的存储器（202）和控制装置（204,210,214）。 所述芯片还包括用于执行至少一个测试过程的测试装置（118,120,220,225,230），所述测试装置包括由所述控制装置重复所述操作中的至少一个操作;以及单个访问元件（118） 测试手段。

    ESD protection network on semiconductor circuit structures
    15.
    发明公开
    ESD protection network on semiconductor circuit structures 失效
    ESD-Schutznetzwerk auf Halbleiterschaltungsstrukturen

    公开(公告)号：EP0932202A1

    公开(公告)日：1999-07-28

    申请号：EP97830741.1

    申请日：1997-12-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Colombo, Paolo ,  Mulatti, Jacopo ,  Campardo, Giovanni ,  Maccarrone, Marco ,  Annunziata, Roberto

    IPC: H01L27/00 ,  H01L27/02

    CPC classification number: H01L27/0259 ,  H01L27/0251

    Abstract: The invention relates to an ESD protection network for a CMOS circuit structure integrated in a semiconductor substrate (2) and comprising discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply (Vcc) having a respective primary ground (GND), and from at least one secondary voltage supply (Vcc_IO) having a respective secondary ground (GND_IO). This network comprises essentially:

    a first ESD protection element (15) for an input stage of the circuit structure;
    a second ESD protection element (5) for an output stage of the circuit structure, the first (15) and second (5) protection elements having an input/output terminal (20) of the integrated circuit structure in common;
    at least one ESD protection element (B0) between the primary supply (Vcc) and the primary ground (GND);
    at least one ESD protection element (B) between the secondary supply (Vcc_IO) and the secondary ground (GND_IO).

    Abstract translation: 本发明涉及一种用于集成在半导体衬底（2）中的CMOS电路结构的ESD保护网络，其包括形成在彼此电绝缘的各个衬底部分中的独立电路块，并且由至少一个初级电压源（Vcc ）具有相应的初级接地（GND），以及具有相应次级接地（GND_IO）的至少一个次级电压源（Vcc_IO）。 该网络基本上包括：用于电路结构的输入级的第一ESD保护元件（15） 用于所述电路结构的输出级的第二ESD保护元件（5），所述第一保护元件（15）和第二保护元件（5）具有所述集成电路结构的输入/输出端子（20）; 主电源（Vcc）和主接地（GND）之间的至少一个ESD保护元件（B0）; 在次级电源（Vcc_IO）和次级接地（GND_IO）之间的至少一个ESD保护元件（B）。

    Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory
    16.
    发明公开
    Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 失效
    方法和电路，用于产生一个地址转换信号ATD以调节访问非易失性存储器

    公开(公告)号：EP0915477A1

    公开(公告)日：1999-05-12

    申请号：EP97830576.1

    申请日：1997-11-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maccarrone, Marco ,  Zammattio, Matteo

    IPC: G11C8/00

    CPC classification number: G11C8/18

    Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells.
    The method consists of duplicating the ATD signal into at least one pair of signals (ATD1,ATD2) and propagating such signals through separate parallel timing chains (6,9) at the ends of which the ATD signal is reinstated, the chains (6,9) being alternately active.

    Abstract translation: 本发明涉及一种方法和用于产生用于半导体集成电子存储器装置的定时存储单元读取相的脉冲同步信号（ATD）的电路。 的脉冲信号（ATD）在检测到所述存储单元的地址输入端的多个的至少一个的逻辑状态的变化的产生。 该ATD信号复制到至少一个对信号（ATD1，ATD2），并通过ATD信号纯粹是表示在其端部的分开的平行的定时链（6,9）传播搜索信号的方法besteht，所述链（6， 9）交替地处于活动状态。

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