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    Non-volatile memory device with row redundancy
    13.
    发明公开
    Non-volatile memory device with row redundancy 有权
    UnflüchtigerSpeicher mit Zeilenredundanz

    公开(公告)号：EP1052572A1

    公开(公告)日：2000-11-15

    申请号：EP99830286.3

    申请日：1999-05-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Manstretta, Alessandro ,  Micheloni, Rino

    IPC: G06F11/20

    CPC classification number: G11C29/846

    Abstract: Non-volatile memory device organised with memory cells that are arranged by row and by column, comprising at least a sector of matrix cells (100), row decoders (D) and column decoders suitable to decode address signals and to activate respectively said rows or said columns, at least a sector of redundancy cells (110) such that it is possible to substitute a row of said sector of matrix cells with a row of said sector of redundancy cells. Said non-volatile memory device comprises a local column decoder (L) for said matrix sector (100) and a local column decoder (L) for said redundancy sector (110). The local column decoders (L) are controlled by external signals so that said row of said redundancy sector (110) is activated simultaneously with said row of said matrix sector (100).

    Abstract translation: 具有由行和列排列的存储单元组织的非易失性存储器件，包括至少一个矩阵单元（100）的扇区，行解码器（D）和适于解码地址信号的列解码器，并分别激活所述行或 所述列，至少一个冗余单元（110）的扇区，使得可以用所述冗余单元扇区的行来代替矩阵单元的所述扇区的一行。 所述非易失性存储器件包括用于所述矩阵扇区（100）的本地列解码器（L）和用于所述冗余扇区（110）的本地列解码器（L）。 本地列解码器（L）由外部信号控制，使得所述冗余扇区（110）的所述行与所述矩阵扇区（100）的所述行同时激活。

    Monolithically integrated selector for electrically programmable memory cells devices
    14.
    发明公开
    Monolithically integrated selector for electrically programmable memory cells devices 失效
    Monolithisch integrierter Umschalterfürelektrisch programmierbare Speicherzellenvorrichtungen

    公开(公告)号：EP0961288A1

    公开(公告)日：1999-12-01

    申请号：EP98830332.7

    申请日：1998-05-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Manstretta, Alessandro ,  Pierin, Andrea ,  Torelli, Guido

    IPC: G11C16/06

    CPC classification number: G11C16/12

    Abstract: A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal (OUT).
    First (P1) and second (P2) field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node (BODY) which is coupled to the first and second voltage generators through a bias circuit block (WBC) effective to bias the node to the higher of the instant voltages generated by the first and second generators.

    Abstract translation: 选择器开关单片集成到用于电可编程存储器单元器件的CMOS工艺电路，其具有至少分别用于耦合到第一和第二电压发生器（HV和LV）的第一和第二输入端子以及输出端子（OUT）。 第一（P1）和第二（P2）场效应选择晶体管分别经由第一和第二端子在第一输入端和输出端之间以及第二输入端和输出端之间连接。 这些晶体管以不重叠的相位被驱动通过控制端子，并且具有连接在体电路节点（BODY）的主体端子，其通过偏置电路块（WBC）耦合到第一和第二电压发生器，该偏置电路块有效地将节点偏置到 由第一和第二发生器产生的瞬时电压越高。

    Staircase adaptive voltage generator circuit
    15.
    发明公开
    Staircase adaptive voltage generator circuit 失效
    Adaptiver Treppenspannungserzeugerstromkreis

    公开(公告)号：EP0862270A1

    公开(公告)日：1998-09-02

    申请号：EP97830084.6

    申请日：1997-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele, Vincenzo ,  Manstretta, Alessandro ,  Rolandi, Paolo ,  Torelli, Guido

    IPC: H03K4/02 ,  G05F1/46

    CPC classification number: G05F1/465 ,  H03K4/023

    Abstract: A stair-case adaptive voltage generator circuit, which circuit comprises a first capacitor (CB) connected between a first voltage reference (Vref) and an output operational amplifier (CA), through first (T1 and second (T4) switches, respectively.
    The terminals of the capacitor are also connected to a second voltage reference (Vinit) through third (T3) and fourth (T2) switches, respectively.
    A second capacitor (CA), in series with a fifth switch (CNT), is connected in parallel to the first capacitor (CB).

    Abstract translation: 一个阶梯式自适应电压发生器电路，该电路包括分别通过第一（T1和第二（T4）开关连接在第一电压基准（Vref）和输出运算放大器（CA）之间的第一电容器（CB）。 电容器的端子也分别通过第三（T3）和第四（T2）开关连接到第二参考电压（Vinit），与第五开关（CNT）串联的第二电容器（CA）并联 到第一个电容（CB）

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