Abstract:
Non-volatile memory device organised with memory cells that are arranged by row and by column, comprising at least a sector of matrix cells (100), row decoders (D) and column decoders suitable to decode address signals and to activate respectively said rows or said columns, at least a sector of redundancy cells (110) such that it is possible to substitute a row of said sector of matrix cells with a row of said sector of redundancy cells. Said non-volatile memory device comprises a local column decoder (L) for said matrix sector (100) and a local column decoder (L) for said redundancy sector (110). The local column decoders (L) are controlled by external signals so that said row of said redundancy sector (110) is activated simultaneously with said row of said matrix sector (100).
Abstract:
A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal (OUT). First (P1) and second (P2) field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node (BODY) which is coupled to the first and second voltage generators through a bias circuit block (WBC) effective to bias the node to the higher of the instant voltages generated by the first and second generators.
Abstract:
A stair-case adaptive voltage generator circuit, which circuit comprises a first capacitor (CB) connected between a first voltage reference (Vref) and an output operational amplifier (CA), through first (T1 and second (T4) switches, respectively. The terminals of the capacitor are also connected to a second voltage reference (Vinit) through third (T3) and fourth (T2) switches, respectively. A second capacitor (CA), in series with a fifth switch (CNT), is connected in parallel to the first capacitor (CB).