-
11.发明授权Method and device for improving convergence time in correlation-based algorithms 有权在基于相关的算法中改善收敛时间的方法和装置公开(公告)号：US08836558B1
公开(公告)日：2014-09-16
申请号：US13897604
申请日：2013-05-20
Applicant: Ahmed Mohamed Abdelatty Ali
Inventor： Ahmed Mohamed Abdelatty Ali
CPC classification number: H03M1/1071 , H03M1/00 , H03M1/0641 , H03M1/0695 , H03M1/1009 , H03M1/12 , H03M1/164 , H03M1/44 , H03M2201/4135
Abstract: A method and a corresponding device reduce the convergence time of a correlation algorithm that uses random signals injected into an analog-to-digital converter (ADC) as input to the algorithm. The method and device involve, at a processor of a pipelined ADC, injecting a random signal into each of a plurality of stages in the pipeline and obtaining digital values generated in response to the random signals. Noise components of residue signals in the plurality of stages are calculated as a function of the digital values and values of the random signals. The noise components correspond to the random signals.
Abstract translation: 一种方法和相应的器件减少了使用注入模数转换器（ADC）的随机信号作为算法输入的相关算法的收敛时间。 该方法和装置涉及在流水线式ADC的处理器处，将随机信号注入流水线中的多个级中的每一级，并获得响应于随机信号产生的数字值。 作为随机信号的数字值和值的函数计算多个级中的残留信号的噪声分量。 噪声分量对应于随机信号。
-
公开(公告)号：US08779959B1
公开(公告)日：2014-07-15
申请号：US13906351
申请日：2013-05-31
Applicant: Wen-Hsien Chuang , Hsiang-Wei Liu , Jen-Wei Tsai , Ting-Hao Wang
Inventor： Wen-Hsien Chuang , Hsiang-Wei Liu , Jen-Wei Tsai , Ting-Hao Wang
CPC classification number: H03M1/0665 , G06F1/10 , H03L7/0814 , H03M1/00 , H03M1/747 , H03M2201/4135
Abstract: A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.
Abstract translation: 公开了一种降低数模转换器（DAC）和实现所述方法的DAC的积分非线性（INL）的方法。 本发明的方法是伪动态元素匹配（PDEM）方法。 与现有技术相比，本发明的方法提供了更好的毛刺性能。 与另一现有技术相比，本发明的方法也保证即使输入的数字代码保持恒定，DEM也不会失效。
-
13.发明授权Charge-transfer coded-voltage generator for use in analog-digital coders and decoders 失效电荷传输编码电压发生器，用于模拟数字编码器和解码器
公开(公告)号：US4350976A
公开(公告)日：1982-09-21
申请号：US215134
申请日：1980-12-10
Applicant: Roger Benoit-Gonin , Jean L. Berger , Jean L. Coutures
Inventor： Roger Benoit-Gonin , Jean L. Berger , Jean L. Coutures
CPC classification number: H03M1/00 , H03M2201/02 , H03M2201/2241 , H03M2201/2266 , H03M2201/2291 , H03M2201/3105 , H03M2201/3178 , H03M2201/4135 , H03M2201/4212 , H03M2201/4233 , H03M2201/4262 , H03M2201/81 , H03M2201/8128 , H03M2201/814 , H03M2201/837
Abstract: Successive two-trip traversals of charges between gates G.sub.0 and G.sub.2 make it possible to obtain beneath gates G.sub.1 and G.sub.2 quantities of charges equal to Q.sub.R, Q.sub.R /2, Q.sub.R /2.sup.2 . . . Q.sub.R /2.sup.i. A readout device for reading charges and connected to gates G.sub.2 and G.sub.4 generates voltages V.sub.R and V.sub.Ri =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.i-1 .multidot.V.sub.R /2.sup.i-1 +V.sub.R /2.sup.i which are compared with a voltage sample V.sub.x to be coded in order to determine by successive approximations the coefficients a.sub.0 . . . a.sub.n which are equal to 0 or to 1 such that V.sub.x =a.sub.0 .multidot.V.sub.R +a.sub.1 .multidot.V.sub.R /2+ . . . +a.sub.n .multidot.V.sub.R /2.sup.n. Depending on the value of a.sub.i, each quantity of charges Q.sub.R /2.sup.i stored beneath gate G.sub.1 is removed beneath diode D.sub.e or stored beneath gate G.sub.3 and then transferred beneath gate G.sub.4.
Abstract translation: 栅极G0和G2之间的电荷的连续两次跳变使得可以获得栅极G1和G2之下的等于QR，QR / 2，QR / 22的电荷量。 。 。 QR / 2i 用于读取电荷并连接到门G2和G4的读出装置产生电压VR和VRi = a0xVR + a1xVR / 2 +。 。 。 + ai-1xVR / 2i-1 + VR / 2i，其与要编码的电压采样Vx进行比较，以便通过逐次逼近来确定系数a0。 。 。 a等于0或1，使得Vx = a0xVR + a1xVR / 2 +。 。 。 + anxVR / 2n。 根据ai的值，存储在栅极G1下方的每个电荷量QR / 2i在二极管De下方被去除或存储在栅极G3下方，然后在栅极G4下方传送。
-
14.发明授权Amplifier for analogue signal samples with automatic gain control, and circuit for digitisation of such samples 失效具有自动增益控制的模拟信号样本的放大器，以及这些样本的数字化电路
公开(公告)号：US3936819A
公开(公告)日：1976-02-03
申请号：US322333
申请日：1973-01-10
Applicant: Philippe Angelle , Georges Lefevre
Inventor： Philippe Angelle , Georges Lefevre
CPC classification number: H03M1/00 , G11C27/026 , H03F3/72 , H03M2201/01 , H03M2201/14 , H03M2201/16 , H03M2201/2241 , H03M2201/2283 , H03M2201/4105 , H03M2201/4135 , H03M2201/4204 , H03M2201/4212 , H03M2201/4233 , H03M2201/4262 , H03M2201/534 , H03M2201/712 , H03M2201/715 , H03M2201/8124
Abstract: An electronic device for amplifying, with automatic gain control by discr values, analogue signal samples and thereafter preferably effecting analogue-to-digital conversion of the samples, consists of an amplifier circuit, a comparator circuit, and a delay store circuit. The amplifier has a basic gain during a gain control or gain ranging operation, and supplies an output sample amplified with sufficient gain to bring it into the region of a predetermined voltage. The comparator circuit compares the output of the amplifier circuit with a reference and supplies an output in accordance with the result of the comparison. For analogue-to-digital conversion the amplifier circuit supplies for an input signal U an output signal 2U - VQ, where VQ is the quantification voltage, or, in other embodiments a signal 2U.
Abstract translation: 用于通过离散值的自动增益控制来放大模拟信号样本的电子装置，其后优选地进行样本的模数转换，由放大器电路，比较器电路和延迟存储电路组成。 放大器在增益控制或增益测距操作期间具有基本增益，并且以足够的增益提供放大的输出样本，使其进入预定电压的区域。 比较器电路将放大器电路的输出与参考值进行比较，并根据比较结果提供输出。 对于模拟到数字转换，放大器电路为输入信号U提供输出信号2U-VQ，其中VQ是量化电压，或者在其它实施例中为信号2U。
-
公开(公告)号：US09215106B2
公开(公告)日：2015-12-15
申请号：US14221968
申请日：2014-03-21
Applicant: LSI Corporation
Inventor： Chaitanya Palusa , Adam B. Healey , Hiep T. Pham , Volodymyr Shvydun
CPC classification number: H04L25/03057 , H03H2218/06 , H03M1/00 , H03M1/14 , H03M2201/4135 , H04L1/06
Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.
Abstract translation: 公开了一种用于校正码间干扰的多级系统和方法。 该系统包括被配置为对输入信号进行采样以产生第一组估计数据位的第一估计模块。 该系统还包括第二估计模块，其被配置为对由预定相移单元移位的输入信号相位进行采样以产生第二组估计数据位，其中第二组估计数据位至少部分地基于第一组产生 的估计数据位和至少一个前置标准系数。
-
Patent Agency Ranking
16.发明申请公开(公告)号：US20150236875A1
公开(公告)日：2015-08-20
申请号：US14221968
申请日：2014-03-21
Applicant: LSI Corporation
Inventor： Chaitanya Palusa , Adam B. Healey , Hiep T. Pham , Volodymyr Shvydun
IPC: H04L25/03
CPC classification number: H04L25/03057 , H03H2218/06 , H03M1/00 , H03M1/14 , H03M2201/4135 , H04L1/06
Abstract: A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.
Abstract translation: 公开了一种用于校正码间干扰的多级系统和方法。 该系统包括被配置为对输入信号进行采样以产生第一组估计数据位的第一估计模块。 该系统还包括第二估计模块，其被配置为对由预定相移单元移位的输入信号相位进行采样以产生第二组估计数据位，其中第二组估计数据位至少部分地基于第一组产生 的估计数据位和至少一个前置标准系数。
-
公开(公告)号：US08994563B2
公开(公告)日：2015-03-31
申请号：US13968036
申请日：2013-08-15
Applicant: Infineon Technologies AG
Inventor： Heimo Hartlieb , Clemens Kain , Michael Hausmann
CPC classification number: H03M1/34 , H03M1/00 , H03M1/001 , H03M1/12 , H03M1/124 , H03M1/129 , H03M1/46 , H03M2201/4135
Abstract: In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.
Abstract translation: 根据实施例，用于操作信号转换器的方法包括将模拟输入信号转换成数字输出信号，包括通过将模拟输入信号与模拟比较信号进行比较，以及检测模拟输入信号是否超过预定的最大值 通过将模拟输入信号与模拟阈值信号进行比较来获得最小阈值。 模拟比较信号和模拟阈值信号由相同的数模转换器产生。
-
公开(公告)号：US20140355650A1
公开(公告)日：2014-12-04
申请号：US13904649
申请日：2013-05-29
Applicant: Intel IP Corporation
Inventor： Merit Hong , David Harnishfeger , Kris Kaufman
IPC: G01K7/16
CPC classification number: G01K7/16 , G01K7/22 , H03M1/0617 , H03M2201/4135
Abstract: A temperature measurement system is disclosed. In accordance with some embodiments of the present disclosure, a temperature measurement system may comprise a resistor, a thermistor, a resistance-to-current converter configured to generate a current signal based on a resistance, an analog-to-digital converter (ADC) configured to receive a first current signal based on the resistor, convert the first current signal into a first digital signal, receive a second current signal based on the thermistor, and convert the second current signal into a second digital signal, and a calculation stage communicatively coupled to an ADC output and configured to determine a first digital value based on the first digital signal, determine a second digital value based on the second digital signal, calculate a resistance ratio based on the first digital value and the second digital value, and determine a temperature output value based on the resistance ratio.
Abstract translation: 公开了一种温度测量系统。 根据本公开的一些实施例，温度测量系统可以包括电阻器，热敏电阻器，被配置为基于电阻产生电流信号的电阻 - 电流转换器，模数转换器（ADC） 被配置为基于所述电阻器接收第一电流信号，将所述第一电流信号转换为第一数字信号，基于所述热敏电阻接收第二电流信号，并将所述第二电流信号转换为第二数字信号，以及计算阶段 耦合到ADC输出并且被配置为基于第一数字信号确定第一数字值，基于第二数字信号确定第二数字值，基于第一数字值和第二数字值计算电阻比，并且确定 基于电阻比的温度输出值。
-
19.发明授权Transmitter for forming non-linear pulse code modulated samples of analog signals by timing the integral of signal samples 失效用于形成模拟信号的非线性脉冲代码调制样本的发送器通过定时信号样本的整合
公开(公告)号：US4010422A
公开(公告)日：1977-03-01
申请号：US409425
申请日：1973-10-25
Applicant: Kornelis Jan Wouda
Inventor： Kornelis Jan Wouda
CPC classification number: H04B14/04 , H03M1/00 , H04B14/048 , H03M2201/01 , H03M2201/14 , H03M2201/16 , H03M2201/196 , H03M2201/2344 , H03M2201/4105 , H03M2201/4135 , H03M2201/4204 , H03M2201/4212 , H03M2201/4225 , H03M2201/4233 , H03M2201/425 , H03M2201/4262 , H03M2201/52 , H03M2201/523 , H03M2201/534 , H03M2201/60 , H03M2201/6121 , H03M2201/712 , H03M2201/715 , H03M2201/8124
Abstract: A non-linear pulse code modulator wherein input signals are coded into digital representations of amplitude range segments and amplitude in excess of the minimum amplitude within the respective range segment uses a first analog-to-digital converter having a sawtooth-shaped control characteristic to determine the amplitude range segment from an input signal sample. The output of the first analog-to-digital converter is used to effectively divide the signal sample by a factor 2.sup.n, where n corresponds to the determined range. The result of the division is then converted in a second analog-to-digital conversion to a digital signal that is combined with the digital range segment signal for transmission thereof.
-
公开(公告)号：JP2018511258A
公开(公告)日：2018-04-19
申请号：JP2017550521
申请日：2016-03-16
Applicant: シーラス ロジック,インコーポレイテッド , Cirrus Logic,Inc.
Inventor： ダス、テジャスヴィ , メランソン、ジョン エル.
CPC classification number: H04R3/04 , G10L19/167 , G10L21/0324 , H03G7/007 , H03G9/005 , H03M1/00 , H03M1/12 , H03M1/1225 , H03M1/18 , H03M2201/4135 , H04L1/20 , H04L27/2647 , H04R2430/01 , H04R2430/03
Abstract: 本開示の実施形態によれば、ダイナミックレンジ拡張情報を有する音声信号を2つ以上の集積回路にわたって処理するためのマルチチップ回路が、ホスト集積回路およびクライアント集積回路を含んでもよい。ホスト集積回路は、デジタル音声入力信号のためのダイナミックレンジ拡張利得を判断し、そのダイナミックレンジ拡張利得に応じてデジタル音声入力信号を処理し、処理済みのデジタル音声入力信号に基づいて音声データを送信するように構成されてもよい。クライアント集積回路はホスト集積回路に結合されてもよく、音声データを受信するように構成されてもよく、クライアント集積回路にダイナミックレンジ拡張利得が提供され、クライアント集積回路はダイナミックレンジ拡張利得を使用して音声データを処理するように構成される。
-
-
-
-
-
-
-
-
-
Search Results
29
records
(took 0.019 seconds)
