公开(公告)号：KR1020110072203A

公开(公告)日：2011-06-29

申请号：KR1020090129043

申请日：2009-12-22

Applicant: 이타칩스 주식회사

Inventor： 서준호 ,  현필수

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/1028 ,  H03M1/38 ,  H03M2201/2233 ,  H03M2201/93

Abstract: PURPOSE: An analog-digital converter having an offset voltage correction function is provided to reduce load of a D/A conversion part, by separating an offset voltage correction part from the D/A conversion part. CONSTITUTION: A D/A conversion part(310) converts a digital signal of N bits into an analog voltage. An offset voltage correction part(360) corrects an offset voltage in the analog-digital converter. A comparator(350) compares an output voltage of the D/A conversion part with an output voltage of the offset voltage correction part. The comparator generates a comparison output voltage. A successive approximation register(370) decides the level of the output voltage of the D/A conversion part, by receiving the comparison output voltage.

Abstract translation: 目的：提供具有偏移电压校正功能的模拟数字转换器，通过将偏移电压校正部分与D / A转换部分离开来减小D / A转换部分的负载。 构成：D / A转换部（310）将N位的数字信号转换为模拟电压。 偏移电压校正部（360）校正模拟数字转换器中的偏移电压。 比较器（350）将D / A转换部分的输出电压与偏移电压校正部分的输出电压进行比较。 比较器产生比较输出电压。 逐次逼近寄存器（370）通过接收比较输出电压来决定D / A转换部分的输出电压的电平。

公开(公告)号：KR1020090116942A

公开(公告)日：2009-11-12

申请号：KR1020080042774

申请日：2008-05-08

Applicant: 연세대학교 산학협력단 ,  동국대학교 산학협력단

Inventor： 김재석 ,  송민규 ,  정민호 ,  문준호 ,  이두복

IPC: H03M1/12

CPC classification number: H03M1/368 ,  H03M1/002 ,  H03M1/121 ,  H03M2201/2208 ,  H03M2201/62 ,  H03M2201/93

Abstract: PURPOSE: A folding-interpolating analog to a digital converter using a less track-and-hold circuit is provided to reduce a circuit area and power consumption by connecting a track-and-hold circuit at the end of a folding block stage. CONSTITUTION: In a folding-interpolating analog to a digital converter using a less track-and-hold circuit, a preamplifier stage(210) amplifies an analog signal by using a plurality of reference voltages and produces a plurality of input signals. A folding block stage(230) folds the input signals according to a predetermined folding rate. The folding block stage produces a plurality of folding signals. The track-and-hold stage(250) is arranged at the backend of the folding block stage by receiving the outputs of the folding block stage. The track-and-hold stage track and holds the folding signals.

Abstract translation: 目的：提供使用较少轨道和保持电路的数字转换器的折叠内插模拟，以通过在折叠块级结束时连接跟踪和保持电路来减少电路面积和功耗。 构成：在使用较少轨道和保持电路的数字转换器的折叠内插模拟中，前置放大器级（210）通过使用多个参考电压来放大模拟信号并产生多个输入信号。 折叠台阶（230）根据预定的折叠速率折叠输入信号。 折叠台阶产生多个折叠信号。 跟踪保持阶段（250）通过接收折叠块阶段的输出而被布置在折叠块阶段的后端。 跟踪和保持阶段跟踪并保存折叠信号。

公开(公告)号：KR1020080102561A

公开(公告)日：2008-11-26

申请号：KR1020070049166

申请日：2007-05-21

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 김수환 ,  양한 ,  우종관

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/002 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/93

Abstract: A signal converter and a method for converting a signal reduce power consumption and a layout area by applying a sharing technique and a switching technique together. A signal converter(100) includes a first amplifier always maintaining the active state, and a third amplifier maintaining the active state in a first phase and a second amplifier maintaining the active state in a second phase. While a plurality of first capacitors(C1) sample the input signal in the first phase, the serially connected first amplifier and the third amplifier amplify the voltage generated by the first voltage set. While a plurality of second capacitors(C2) sample the output voltage of the second amplifier in the second phase, the serially connected first amplifier and the second amplifier amplify the voltage generated by the second voltage set.

Abstract translation: 信号转换器和用于转换信号的方法通过共享技术和切换技术共同地降低功耗和布局面积。 信号转换器（100）包括总是维持有效状态的第一放大器和保持第一相位中的有效状态的第三放大器和保持第二阶段的激活状态的第二放大器。 当多个第一电容器（C1）在第一相中对输入信号进行采样时，串联的第一放大器和第三放大器放大由第一电压组产生的电压。 当多个第二电容器（C2）在第二相中对第二放大器的输出电压进行采样时，串联的第一放大器和第二放大器放大由第二电压组产生的电压。

公开(公告)号：KR1020050117321A

公开(公告)日：2005-12-14

申请号：KR1020040042605

申请日：2004-06-10

Applicant: 전자부품연구원

Inventor： 이대성 ,  박효덕 ,  김규철 ,  도형욱

IPC: H03M1/38

CPC classification number: H03M1/38 ,  H03M1/1205 ,  H03M1/14 ,  H03M2201/2233 ,  H03M2201/62 ,  H03M2201/93

Abstract: 본 발명은 N 비트 축차근사형 아날로그-디지털 변환 장치(SAR ADC)에 관한 것으로서, 상기 아날로그 신호를 입력받고 N 비트의 디지털 코드에 따라 기준 전압을 분배하여 입력 신호와 비교하며, 상기 비교 결과에 따라 입력 신호에 대응하는 N 비트의 디지털 코드를 비트별로 순차적으로 판정하는 N 비트 축차근사형 아날로그-디지털 변환기와, 상기 N 비트 축차근사형 아날로그-디지털 변환기에 의해 N 비트의 디지털 코드 판정이 완료되면, 판정 오차를 N 비트 축차근사형 아날로그-디지털 변환기에 입력하고 상기 기준 전압을 2
N 배로 분주하며 디지털 코드의 판정이 완료될 때까지 후속 비트를 순차적으로 판정하도록 상기 N 비트 축차근사형 아날로그-디지털 변환기를 제어하는 제어 수단을 포함한다. 본 발명에 따르면, SAR ADC를 단위 블록으로 사용하여 보다 큰 해상도의 SAR ADC를 용이하게 구현할 수 있으며, SAR ADC에서 사용되는 캐패시터의 수와 면적을 감소시켜서 높은 해상도의 SAR ADC를 적은 면적으로 구현할 수 있다.

公开(公告)号：KR1020010026158A

公开(公告)日：2001-04-06

申请号：KR1019990037365

申请日：1999-09-03

Applicant: 엘지전자 주식회사

Inventor： 이우열

IPC: H03M1/06

CPC classification number: H03M1/76 ,  H03M2201/6107 ,  H03M2201/93

Abstract: PURPOSE: A digital/analog converter is provided to obtain 12 bits, high resolution by using the lowest 2-bits as an extension resist-array to output the lower voltage and using the upper 10 bits as the conventional resist-array to output the upper voltage. CONSTITUTION: In a digital/analog converter including a series of resistors(20) which allow a voltage corresponding to a decoded value to be output, an analog voltage correcting unit divides the resistors constructing the resistor series into a plurality of resistor groups for stabilization of output characteristic. The analog voltage correcting unit corrects the voltage of each resistor group to have a uniform voltage variation. The lowest resistor of the resistor series is constructed of an extension resistor series(40) selected by an extension bit.

Abstract translation: 目的：提供数字/模拟转换器，通过使用最低2位作为扩展阻抗阵列来获得12位高分辨率，以输出较低电压，并使用高10位作为常规抗蚀剂阵列输出上层 电压。 构成：在包括允许输出对应于解码值的电压的一系列电阻器（20）的数字/模拟转换器中，模拟电压校正单元将构成电阻器系列的电阻器分成多个电阻器组，以稳定 输出特性。 模拟电压校正单元校正每个电阻组的电压以具有均匀的电压变化。 电阻器系列的最低电阻由扩展位选择的扩展电阻器系列（40）构成。

公开(公告)号：KR1020080114196A

公开(公告)日：2008-12-31

申请号：KR1020070063540

申请日：2007-06-27

Applicant: 에스케이하이닉스 주식회사

Inventor： 정종호 ,  이재진 ,  곽계달 ,  임종만 ,  최재웅 ,  채명준

IPC: H03M1/12

CPC classification number: H03M1/64 ,  H03M1/124 ,  H03M2201/192 ,  H03M2201/831 ,  H03M2201/93

Abstract: An analog-digital converter capable of improving accuracy of conversion operation, on die thermal sensor including the same, and implementing method thereof are provided to facilitate application in a DRAM(Dynamic Random Access Memory) etc by not requiring a charge pump. An analog-digital converter capable of improving accuracy of conversion operation comprises an integrating part(420) and a counting part(430). The integrating part integrates a conversion object voltage having a positive value in a reverse terminal and a first voltage higher than the conversion object voltage in a non-reverse terminal with a positive slope during a predetermined time. The integrating part outputs and integrates a second voltage higher than the first voltage instead of the conversion object voltage in the reverse terminal with a negative slope after the predetermined time. The counting part outputs a digital code by counting a time that an output voltage of the integrating part falls down to a specified level.

Abstract translation: 提供了一种能够提高转换操作精度的模拟数字转换器，包括其的芯片热敏传感器及其实现方法，以便于不需要电荷泵便于在DRAM（动态随机存取存储器）等中应用。 能够提高转换操作精度的模拟数字转换器包括积分部件（420）和计数部件（430）。 积分部在预定时间内积分反向端子中具有正值的转换对象电压和高于非反向端子中的转换对象电压的第一电压，具有正斜率。 在预定时间之后，积分部分输出并积分高于第一电压的第二电压，而不是反向端子中的转换对象电压为负斜率。 计数部通过对积分部的输出电压下降到指定电平的时间进行计数来输出数字码。

公开(公告)号：KR1020070024002A

公开(公告)日：2007-03-02

申请号：KR1020050078442

申请日：2005-08-25

Applicant: 엘지전자 주식회사

Inventor： 임종철

IPC: H03M1/12

CPC classification number: H03M1/145 ,  H03M1/002 ,  H03M1/50 ,  H03M2201/11 ,  H03M2201/76 ,  H03M2201/93

Abstract: A pipeline type analog-to-digital converter is provided to prevent a linearity problem according to a reduction of resolution. In a pipeline type analog-to-digital converter, a sample and hold amplifier receives an analog input signal and holds a voltage corresponding to a voltage level of the analogue input signal in a sample cycle during a determined time cycle. An analog to digital converter converts the analog input signal held in the sample and hold amplifier to a digital signal. A multiplying digital to analog converter comprises a digital to analog converter to convert the generated digital signal of the analog to digital converter into a middle analog signal, a sigma synthesizer to deduct the middle analog signal value from the analog input signal held in the sample and hold amplifier, and a mixer to mix the signal deducted by the sigma synthesizer with a clock. A sampling cycle and an amplification cycle of the clock applied to the multiplying digital to analog converter are 25% and 75% respectively. Each cycle is converted by an internal clock conversion unit including a clock oscillator(410), a first buffer(420), a frequency delayer(430), and a second buffer(440).

Abstract translation: 提供了一种流水线型模拟 - 数字转换器，以根据分辨率的降低来防止线性问题。 在流水线型模数转换器中，采样和保持放大器在确定的时间周期内接收模拟输入信号并且在采样周期中保持与模拟输入信号的电压电平相对应的电压。 模数转换器将采样和保持放大器中保持的模拟输入信号转换为数字信号。 乘法数模转换器包括数模转换器，用于将所产生的模拟数字转换器的数字信号转换为中间模拟信号，西格马合成器从保持在样本中的模拟输入信号中扣除中间模拟信号值;以及 保持放大器和混频器将由Σ合成器扣除的信号与时钟进行混合。 施加到倍增数模转换器的时钟的采样周期和放大周期分别为25％和75％。 每个周期由包括时钟振荡器（410），第一缓冲器（420），频率延迟器（430）和第二缓冲器（440）的内部时钟转换单元转换。

公开(公告)号：KR1020060079379A

公开(公告)日：2006-07-06

申请号：KR1020040117528

申请日：2004-12-30

Applicant: 동부일렉트로닉스 주식회사

Inventor： 이영성

IPC: H03M1/06 ,  H03M1/66

CPC classification number: H03M1/0609 ,  H03M1/1009 ,  H03M1/66 ,  H03M2201/62 ,  H03M2201/93

Abstract: 재생 가능한 디지털 아날로그 변환기가 개시된다. 본 발명에 따른 디지털 아날로그 변환기는 디지털 아날로그 변환기 출력의 정밀 제어를 위하여 비교 증폭기를 구비한 기준 셀(reference cell), 기준 셀에서 출력되는 연산값과 대비하여 신호변환을 수행하는 디지털 아날로그 변환기 서브 셀(sub cell), 및 디지털 아날로그 변환기 서브 셀의 전원라인(power line) 사이에 삽입되어 저항값을 보정할 수 있는 저항 보정 회로로 구성된다. 전원라인 사이에 삽입되는 저항 보정 회로는, 하층에 다수인 N개의 배선이 병렬로 형성되어 있는 금속배선들, 및 하층의 금속배선들과 상층의 전원라인을 전기적으로 연결하는 콘택플러그들을 포함하여 최대값 밸런스 불량(full scale balance fail)이 발생한 경우에 n개의 금속배선을 잘라서 n/N(Nn)의 비율로 저항을 상승시켜 칩을 재생시킬 수 있다.
디지털 아날로그 변환기, 최대값 밸런스, 기준 셀, 저항 보정 회로

公开(公告)号：KR1020010046173A

公开(公告)日：2001-06-05

申请号：KR1019990049839

申请日：1999-11-11

Applicant: 에스케이하이닉스 주식회사

Inventor： 김사현

IPC: H03M1/12

CPC classification number: H03M1/468 ,  H03M2201/93

Abstract: PURPOSE: An analog/digital converter of successive approximation type is provided to carry out the same function as an existing analog/digital converter of successive approximation type with using half of a device composing a ladder portion and a decoder. CONSTITUTION: An analog/digital converter of successive approximation type includes a holding register(20b), a shift register(20a), a decoding register(20c), a ladder portion(30c), a power control portion(40), a decoder(30a) and a voltage comparator(10). The holding register(20b) stores the data of n bit. The shift register(20a) controls the holding register(20b) in order. The decoding register(20c) outputs each bit except for the highest rank bit and the lowest rank bit of the holding register(20b) with using an inverting or non-inverting method. The ladder portion(30c) forms the output step outputting voltage of each node. The power control portion(40) changes the route of the supplying voltage and the reference voltage selectively and supplies it with the forward voltage or the inverse voltage. The decoder(30a) inputs the output of the decoding register(20c) and the lowest rank bit of the holding register(20b) and turns on a switching device of the ladder portion(30c) selectively. The voltage comparator(10) compares the voltage output from the ladder portion(30c) with the sampled voltage of the analog signal and outputs the result with the logic value of the binary scale.

Abstract translation: 目的：提供逐次逼近型的模拟/数字转换器，以实现与现有的逐次逼近型模拟/数字转换器相同的功能，使用构成梯形部分和解码器的器件的一半。 构成：逐次逼近型的模拟/数字转换器包括保持寄存器（20b），移位寄存器（20a），解码寄存器（20c），梯形部分（30c），功率控制部分（40），解码器 （30a）和电压比较器（10）。 保持寄存器（20b）存储n位的数据。 移位寄存器（20a）按顺序控制保持寄存器（20b）。 解码寄存器（20c）使用反相或非反相方法输出除保持寄存器（20b）的最高位和除最低位以外的每个位。 梯形部分（30c）形成输出步骤，输出每个节点的电压。 功率控制部分（40）选择性地改变供电电压和参考电压的路径，并向其提供正向电压或反向电压。 解码器（30a）输入解码寄存器（20c）的输出和保持寄存器（20b）的最低等级位，并选择性地导通梯形部分（30c）的开关装置。 电压比较器（10）将来自梯形部分（30c）的电压与模拟信号的采样电压进行比较，并将结果输出到二进制标度的逻辑值。

公开(公告)号：KR1020000042418A

公开(公告)日：2000-07-15

申请号：KR1019980058583

申请日：1998-12-24

Applicant: 에스케이하이닉스 주식회사

Inventor： 배종홍

IPC: H03M1/66

CPC classification number: H03M1/38 ,  H03M2201/814 ,  H03M2201/93

Abstract: PURPOSE: An analog-to-digital converting circuit is provided to optimize an analog-to-digital conversion time. CONSTITUTION: An analog-to-digital converting circuit comprises a plurality of analog switches, which selects and outputs one of voltages(V0.8,V1.4,V2.2,V3.1) in response to a 3-bit SAR input signal(SAR£1:3|) of a 4-bit SAR input signal(SAR£1:4|) from an SAR register and a signal(ST£1:4|) indicating a conversion cycle from a digital-to-analog conversion to an analog-to-digital conversion. In an analog-to-digital converting circuit, a final path is previously determined by use of a value of a previously determined SAR register.

Abstract translation: 目的：提供模数转换电路，以优化模数转换时间。 构成：模数转换电路包括多个模拟开关，其响应于3位SAR输入选择并输出电压（V0.8，V1.4，V2.2，V3.1）中的一个 来自SAR寄存器的4位SAR输入信号（SAR£1：4 |）的信号（SAR£1：3 |）和表示来自数字 - 模拟转换为模数转换。 在模数转换电路中，预先通过使用先前确定的SAR寄存器的值来确定最终路径。