具有反馈桥接器的放大器
    11.
    发明公开

    公开(公告)号:CN1897458A

    公开(公告)日:2007-01-17

    申请号:CN200610092289.X

    申请日:2006-06-16

    Abstract: 一种放大器,特别用于RF应用,包括电路板(2)、具有设置在电路板(2)上的至少一个晶体管封装(8)的至少一个放大器级、以及围绕至少一个晶体管封装(8)的反馈路径(12),所述反馈路径(12)包括具有用于阻止直流电流过反馈路径(12)的至少一个电容元件(C)的反馈元件(15),以及优选地还包括至少一个电感元件(L)和/或电阻元件(R)。为了减少由于长印制反馈线对放大器性能的负面影响,在根据本发明的放大器中的反馈路径由反馈桥接器(9)形成,所述反馈桥接器(9)包括在晶体管封装(8)的两个接触标志(10、11)处从电路板(2)平面引出的两条反馈线(13、14)以及跨接在两条反馈线(13、14)之间的所述晶体管封装上方的反馈元件(15)。

    Ceramic capacitor
    17.
    发明公开
    Ceramic capacitor 有权
    Keramikkondensator

    公开(公告)号:EP1761119A1

    公开(公告)日:2007-03-07

    申请号:EP06018353.0

    申请日:2006-09-01

    Abstract: A circuit board (10, 10", 10"') comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101', 101'', 101 "', 101'''', 101''''', 101'''''') having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101', 101'', 101 "', 101'''', 101''''', 101'''''') being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

    Abstract translation: 一种电路板(10,10“,10”'),包括:具有主芯表面(12)和后芯表面(13)的板芯(11); 具有主电容器表面(102)和后电容器(102)的陶瓷电容器(101,101',101“,101”',101“,101”',101“',101”',101“ 表面(103)具有其中第一内电极层(141)和第二内电极层(142)交替地层叠有陶瓷介电层(105)并且具有多个电容器功能单元( 陶瓷电容器101,101',101“,101”',101“,101”',101“',101”',101“',101”',101“',101” 在主芯表面(12)和主电容器表面(102)指向相同方向的状态下埋在板芯(11)中; 以及具有其中层间绝缘层(33,35)和导体层(42)在主芯面(12)和主电容器表面(102)上交替层叠的结构的积层(31),并具有 半导体集成电路器件安装区域(23,51,52),用于安装在积聚层(31)的表面(39)上具有多个处理器核(24,25)的半导体集成电路器件(21,53,54) ),其中所述多个电容器功能单元(107,108)能够分别电连接到所述多个处理器核(24,25)。

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