리드 플레이트 및 이를 구비하는 보호회로기판
    191.
    发明公开
    리드 플레이트 및 이를 구비하는 보호회로기판 失效
    引导板和保护电路板

    公开(公告)号:KR1020110069367A

    公开(公告)日:2011-06-23

    申请号:KR1020090126076

    申请日:2009-12-17

    Inventor: 김봉영 김영호

    Abstract: PURPOSE: A lead plate and a protection circuit board having the same are provided to improve adhesive strength of a bare cell and a protection circuit board and to facilitate a welding process by laser welding of the bare cell and the protection circuit board. CONSTITUTION: A lead plate connecting a protection circuit board and an external device of a secondary battery includes a mount part(52), a joint part(54) a stepped pulley part(56). The mount part is connected to one side of a printed circuit board. The joint part is connected to the external device. The stepped pulley part connects the mount part and the joint part. The area of the mount part is formed wider than the area welded to the external device.

    Abstract translation: 目的:提供一种引线板及其保护电路板,以提高裸电池和保护电路板的粘合强度,并通过激光焊接裸电池和保护电路板来促进焊接过程。 构成:连接保护电路板和二次电池的外部装置的引线板包括安装部分(52),接合部分(54),阶梯式带轮部分(56)。 安装部分连接到印刷电路板的一侧。 接头部分连接到外部设备。 阶梯式带轮部分连接安装部分和接头部分。 安装部分的区域形成为比焊接到外部设备的区域更宽。

    패키지 구조 및 그의 제조 방법
    192.
    发明公开
    패키지 구조 및 그의 제조 방법 无效
    包装结构及其制造方法

    公开(公告)号:KR1020090059391A

    公开(公告)日:2009-06-11

    申请号:KR1020070126229

    申请日:2007-12-06

    Abstract: A package structure and a manufacturing method thereof are provided to improve storage capacitance while reducing the thickness by stacking the packages in a hole of a printed circuit board. An insulation layer and a conductive pattern are repeatedly laminated in a printed circuit board. The insulation layer includes a core layer and an insulating polymer layer. A penetration hole(104) penetrating from the upper part to the lower part of the print circuit board is equipped in the printed circuit board. Packages(130) are vertically laminated in the penetration hole. A lead frame of the package is bonded in the conductive pattern of the planarization part of the side step of the penetration hole.

    Abstract translation: 提供一种封装结构及其制造方法,以通过将封装堆叠在印刷电路板的孔中来减小厚度来提高存储电容。 在印刷电路板中重复地层压绝缘层和导电图案。 绝缘层包括芯层和绝缘聚合物层。 在印刷电路板中装有从印刷电路板的上部贯穿到下部的贯通孔(104)。 包装(130)在穿孔中垂直层压。 封装的引线框架结合在穿透孔的侧台阶的平坦化部分的导电图案中。

    전자 모듈 및 그 제조방법
    196.
    发明公开
    전자 모듈 및 그 제조방법 无效
    电子模块及其制造方法

    公开(公告)号:KR1020010050124A

    公开(公告)日:2001-06-15

    申请号:KR1020000047838

    申请日:2000-08-18

    Applicant: 사프란

    Abstract: PURPOSE: An electronics module and a method of manufacturing the same is provided to achieve a cooled power electronics module of reduced bulk. CONSTITUTION: An electronics module comprises a metal substrate having a major face that has an insulating layer(12) thereon and that carries a plurality of electrical connection tracks(16) and a non-insulated major face, and at least one power component(18) fixed on the non-insulated major face of the substrate and having connection tabs(20) which pass through the substrate via holes(30) therein and are electrically insulated from the substrate, the tabs being soldered to respective ones of the tracks, and a housing(22) bonded to an inside wall of a cooling fluid circuit, and the component being located inside the housing and in close contact therewith.

    Abstract translation: 目的:提供一种电子模块及其制造方法,以实现减小体积的冷却功率电子模块。 构成:电子模块包括具有主表面的金属基底,该主面在其上具有绝缘层(12)并且承载多个电连接轨道(16)和非绝缘主面,以及至少一个功率部件(18 )固定在基板的非绝缘主面上并且具有通过其中的基板通孔(30)的连接接片(20),并且与基板电绝缘,所述突片被焊接到相应的轨道,并且 结合到冷却流体回路的内壁的壳体(22),并且所述部件位于壳体内并与其紧密接触。

    Stack semiconductor package and a method of producing

    公开(公告)号:KR100874882B1

    公开(公告)日:2008-12-19

    申请号:KR20070058847

    申请日:2007-06-15

    Abstract: 반도체 스택 패키지는 제 1 반도체 패키지, 제 2 반도체 패키지 및 도전성 연결부재를 포함한다. 제 1 반도체 패키지는 제 1 반도체 칩, 상기 제 1 반도체 칩과 전기적으로 연결된 제 1 외부 접속 리드들을 갖는 제 1 리드 프레임, 및 상기 제 1 외부 접속 리드들이 노출되도록 상기 제 1 반도체 칩과 상기 제 1 리드 프레임을 둘러싸는 제 1 봉지부재를 포함한다. 제 2 반도체 패키지는 제 2 반도체 칩, 상기 제 2 반도체 칩과 전기적으로 연결된 제 2 외부 접속 리드들을 갖고 상기 제 1 봉지부재 상에 배치된 제 2 리드 프레임, 및 상기 제 2 외부 접속 리드들이 노출되도록 상기 제 2 반도체 칩과 상기 제 2 리드 프레임을 둘러싸는 제 2 봉지부재를 포함한다. 도전성 연결부재는 상기 제 1 및 제 2 봉지부재들로부터 각각 노출된 상기 제 1 및 제 2 외부 접속 리드들을 전기적으로 연결시킨다. 또한, 도전성 연결부재는 도전성 연결부재에 발생된 크랙의 전진을 차단하는 크랙 차단홈을 갖는다. 따라서, 도전성 연결부재에 발생된 크랙의 전진이 크랙 차단홈에 의해 차단된다.

    STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    199.
    发明公开
    STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 无效
    堆叠式半导体封装及其制造方法

    公开(公告)号:KR20080110285A

    公开(公告)日:2008-12-18

    申请号:KR20070058847

    申请日:2007-06-15

    Abstract: A semiconductor stacked package and a method of manufacture thereof is provided to intercept the advance of the crack generated in the conductive connection member by the crack blocking groove. A semiconductor stacked package(100) comprises a first semiconductor package, a second semiconductor package, and a conductive connection member(300). The first semiconductor package comprises a first semiconductor chip, a first lead frame, and a first sealing cover. The first lead frame has a first outer portion connecting leads electrically connected with the first semiconductor chip. The first sealing cover is formed on the first semiconductor chip and the first lead frame in order to be exposed with the first lead frame and the first outer portion connecting lead. The second semiconductor package comprises a second semiconductor chip, a second lead frame, and a second sealing cover(250). The second lead frame has a second outside connecting leads electrically connected with the second semiconductor chip. The second lead frame is arranged on the first sealing cover. The second sealing cover is formed on the second semiconductor chip and the second lead frame so that the second outside connecting lead is exposed. The conductive connection member electrically connects the first and second outside connecting leads respectively exposed from the first and second sealing covers. The conductive connection member has the crack blocking groove.

    Abstract translation: 提供一种半导体堆叠封装及其制造方法,用于截断通过裂缝阻挡槽在导电连接构件中产生的裂纹的进展。 半导体堆叠封装(100)包括第一半导体封装,第二半导体封装和导电连接构件(300)。 第一半导体封装包括第一半导体芯片,第一引线框架和第一密封盖。 第一引线框架具有连接与第一半导体芯片电连接的引线的第一外部部分。 第一密封盖形成在第一半导体芯片和第一引线框架上,以便与第一引线框架和第一外部部分连接引线一起露出。 第二半导体封装包括第二半导体芯片,第二引线框架和第二密封盖(250)。 第二引线框架具有与第二半导体芯片电连接的第二外部连接引线。 第二引线框架布置在第一密封盖上。 第二密封盖形成在第二半导体芯片和第二引线框架上,使得第二外部连接引线露出。 导电连接构件电连接分别暴露于第一和第二密封盖的第一和第二外部连接引线。 导电连接构件具有裂纹阻挡槽。

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