公开(公告)号：US20150053468A1

公开(公告)日：2015-02-26

申请号：US14532224

申请日：2014-11-04

Applicant: HARRIS CORPORATION

Inventor： MICHAEL RAYMOND WEATHERSPOON ,  LOUIS JOSEPH RENDEK, JR. ,  LAWRENCE WAYNE SHACKLETTE ,  CASEY PHILIP RODRIGUEZ

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/116 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0141 ,  H05K2201/09545 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions.

Abstract translation: 一种从电路板层制造多层电路板的方法，每个电路板包括电介质层和其上包括第一金属的导电迹线。 该方法包括在第一电路板层中形成通孔，将通孔与第一金属电镀，并将第二金属涂覆在第一电路板层的第一金属上，镀通孔和第一金属 金属。 该方法还包括将第一和第二电路板层对准在一起，使得第一电路板层的电镀通孔与第二电路板层上的特征相邻，并且加热并压紧对准的第一和第二电路板层 以将电介质层层合在一起并形成接合相邻金属部分的第一和第二金属的金属间化合物。

公开(公告)号：US08642908B2

公开(公告)日：2014-02-04

申请号：US13202176

申请日：2010-10-13

Applicant: Jonas Moran ,  Mats Kleverman

Inventor： Jonas Moran ,  Mats Kleverman

IPC: H03K17/975

CPC classification number: G06F3/0202 ,  H03K17/9645 ,  H05K1/0275 ,  H05K1/053 ,  H05K1/115 ,  H05K1/116 ,  H05K1/162 ,  H05K1/167 ,  H05K3/0026 ,  H05K3/4015 ,  H05K3/4046 ,  H05K3/445 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/0999 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2203/107

Abstract: An electronic device comprises a housing having an outer face and an inner face. A key is provided on the housing, which comprises a micro hole formed in the housing and a conductive material extending within the micro hole to the outer face of the housing. A sensor is coupled to the conductive material to detect whether an object is brought into contact or out of contact with the micro hole at the outer face.

Abstract translation: 电子设备包括具有外表面和内表面的壳体。 在壳体上设有钥匙，该钥匙包括形成在壳体中的微孔和在微孔内延伸到壳体外表面的导电材料。 传感器耦合到导电材料，以检测物体是否与外表面的微孔接触或脱离接触。

公开(公告)号：US20130244490A1

公开(公告)日：2013-09-19

申请号：US13879883

申请日：2011-11-29

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R31/06 ,  H05K3/12 ,  H05K3/10

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. The electrical interconnect includes a socket substrate with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are bonded to the first surface of the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias are located in the openings that electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pad that are adapted to electrically and mechanically couple the electrical interconnect to the PCB.

Abstract translation: 适于在BGA器件上的焊球和PCB之间提供界面的表面贴装电互连。 电互连包括具有第一表面，第二表面和多个开口的插座基板，其尺寸和构造用于接收BGA器件上的焊球。 多个导电接触片接合到插座衬底的第一表面，使得接触片上的接触尖端延伸到开口中。 当焊球定位在开口中时，接触尖端与BGA器件电耦合。 通孔位于开口中，其将接触片电耦合到位于插座衬底的第二表面附近的接触垫。 焊球被接合到接触焊盘上，适于电连接和机械地将电互连件耦合到PCB。

公开(公告)号：US20130107482A1

公开(公告)日：2013-05-02

申请号：US13665325

申请日：2012-10-31

Applicant: Yasushi INAGAKI ,  Motoo ASAI ,  Dongdong WANG ,  Hideo YABASHI ,  Seiji SHIRAI

Inventor： Yasushi INAGAKI ,  Motoo ASAI ,  Dongdong WANG ,  Hideo YABASHI ,  Seiji SHIRAI

IPC: H05K1/18

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract translation: 印刷电路板包括容纳层，容纳层中容纳的片状电容器器件，以及形成在容纳层上的堆积结构，使得堆积结构覆盖容纳层中的片状电容器器件。 积层结构具有安装导体结构，其被定位成将IC芯片装置安装在积层结构的表面上，使得IC芯片装置直接安装在芯片电容器装置上，每个芯片电容器装置具有电介质体， 所述积聚结构，形成在所述电介质体上且在所述电介质体的表面上延伸的第一电极，以及形成在所述电介质体上并在所述电介质体的表面上延伸的第二电极，并且所述电介质体介于所述第一电极 电极和第二电极。

公开(公告)号：US08418361B2

公开(公告)日：2013-04-16

申请号：US13299685

申请日：2011-11-18

Applicant: Suk Won Lee ,  Chang Gun Oh ,  Mi Sun Hwang

Inventor： Suk Won Lee ,  Chang Gun Oh ,  Mi Sun Hwang

IPC: H05K3/02

CPC classification number: H05K3/421 ,  H05K1/116 ,  H05K3/108 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Method of manufacturing printed circuit board, including: providing a substrate including a first circuit layer having a lower land of a via; forming an insulating layer on the first circuit layer; forming a via hole in the insulating layer; filling the via hole with a first metal, thus forming a via; forming a seed layer with a second metal on the insulating layer and an exposed surface of the via; applying a resist film on the seed layer, and forming a resist pattern having an opening for a second circuit layer with a width formed on the via being smaller than a width of the via; plating a circuit region defined by the opening with a third metal, thus forming a plating layer formed of the third metal; and removing the resist film, and selectively removing an exposed portion of the seed layer, thus forming a second circuit layer.

Abstract translation: 制造印刷电路板的方法，包括：提供包括具有通孔下部的第一电路层的基板; 在所述第一电路层上形成绝缘层; 在绝缘层中形成通孔; 用第一金属填充通孔，从而形成通孔; 在绝缘层上形成具有第二金属的种子层和通孔的暴露表面; 在种子层上施加抗蚀剂膜，并且形成具有形成在通孔上的宽度的第二电路层的开口的抗蚀剂图案小于通孔的宽度; 用第三金属电镀由开口限定的电路区域，从而形成由第三金属形成的镀层; 并去除抗蚀剂膜，并且选择性地去除种子层的暴露部分，从而形成第二电路层。

公开(公告)号：US20130025926A1

公开(公告)日：2013-01-31

申请号：US13644667

申请日：2012-10-04

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wei-Cheng Chen

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit substrate having a base layer, a patterned conductive layer, a dielectric layer and a conductive block is provided. The patterned conductive layer is disposed on the base layer and having an inner pad. The dielectric layer is disposed on the base layer and covering the patterned conductive layer. The conductive block penetrates the dielectric layer, the conductive block being substantially coplanar with the dielectric layer and connecting the inner pad.

Abstract translation: 提供具有基底层，图案化导电层，电介质层和导电块的电路基板。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 导电块穿透电介质层，导电块基本上与电介质层共面并连接内焊盘。

公开(公告)号：US20120066902A1

公开(公告)日：2012-03-22

申请号：US13301063

申请日：2011-11-21

Applicant: Han Kim ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Chang Gun Oh

Inventor： Han Kim ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Chang Gun Oh

IPC: H05K3/10

CPC classification number: H05K1/116 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/025 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2201/09545 ,  Y10T29/49165

Abstract: A method of manufacturing a printed circuit board, including: preparing a double-sided substrate which comprises an insulating layer, a first copper layer formed on one side of the insulating layer and a second copper layer formed on the other side of the insulating layer; forming a via-hole through the second copper layer and the insulating layer; forming a plating layer on an inner wall of the via-hole; and forming, on the double-sided substrate, a via, a first circuit layer including a circuit pattern that is formed on a surface of the via having a minimum diameter and has a line width smaller than the minimum diameter of the via, and a second circuit layer including a lower land.

Abstract translation: 一种制造印刷电路板的方法，包括：制备双面基板，其包括绝缘层，形成在所述绝缘层的一侧上的第一铜层和形成在所述绝缘层的另一侧上的第二铜层; 通过所述第二铜层和所述绝缘层形成通孔; 在所述通孔的内壁上形成镀层; 并且在双面基板上形成通孔，包括形成在具有最小直径并且具有小于通孔的最小直径的线宽度的通孔的表面上的电路图案的第一电路层，以及 第二电路层包括较低的焊盘。

公开(公告)号：US20120060369A1

公开(公告)日：2012-03-15

申请号：US13299685

申请日：2011-11-18

Applicant: Suk Won LEE ,  Chang Gun Oh ,  Mi Sun Hwang

Inventor： Suk Won LEE ,  Chang Gun Oh ,  Mi Sun Hwang

IPC: H01K3/10

CPC classification number: H05K3/421 ,  H05K1/116 ,  H05K3/108 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Method of manufacturing printed circuit board, including: providing a substrate including a first circuit layer having a lower land of a via; forming an insulating layer on the first circuit layer; forming a via hole in the insulating layer; filling the via hole with a first metal, thus forming a via; forming a seed layer with a second metal on the insulating layer and an exposed surface of the via; applying a resist film on the seed layer, and forming a resist pattern having an opening for a second circuit layer with a width formed on the via being smaller than a width of the via; plating a circuit region defined by the opening with a third metal, thus forming a plating layer formed of the third metal; and removing the resist film, and selectively removing an exposed portion of the seed layer, thus forming a second circuit layer.

Abstract translation: 制造印刷电路板的方法，包括：提供包括具有通孔下部的第一电路层的基板; 在所述第一电路层上形成绝缘层; 在绝缘层中形成通孔; 用第一金属填充通孔，从而形成通孔; 在绝缘层上形成具有第二金属的种子层和通孔的暴露表面; 在种子层上施加抗蚀剂膜，并且形成具有形成在通孔上的宽度的第二电路层的开口的抗蚀剂图案小于通孔的宽度; 用第三金属电镀由开口限定的电路区域，从而形成由第三金属形成的镀层; 并去除抗蚀剂膜，并且选择性地去除种子层的暴露部分，从而形成第二电路层。

公开(公告)号：US20110108315A1

公开(公告)日：2011-05-12

申请号：US12835085

申请日：2010-07-13

Applicant: CHEN-YUEH KUNG ,  Wei-Cheng Chen

Inventor： CHEN-YUEH KUNG ,  Wei-Cheng Chen

IPC: H05K1/11 ,  H01B5/14 ,  B29C35/08

CPC classification number: H05K3/4007 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for fabricating a circuit substrate is provided. A patterned conductive layer having an inner pad is provided on a base layer, a dielectric layer is disposed on the base layer and covers the patterned conductive layer, and a covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second opening is formed. Finally, the patterned mask, surplus layer and covering layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 具有内垫的图案化导电层设置在基底层上，电介质层设置在基底层上并覆盖图案化导电层，并且覆盖层设置在电介质层上。 通过干蚀刻去除覆盖层的一部分以形成第一开口。 去除由第一开口暴露的电介质层的一部分，以形成暴露一部分内垫的电介质开口。 在覆盖层上形成具有第二开口以露出内部衬垫的一部分的图案化掩模。 形成包括填充电介质开口的导电块，填充第一开口的外垫和填充第二开口的剩余层的导电结构。 最后，去除图案化掩模，多余层和覆盖层。

公开(公告)号：US07855894B2

公开(公告)日：2010-12-21

申请号：US11928397

申请日：2007-10-30

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract translation: 片状电容器20设置在印刷电路板10中。以这种方式，IC芯片90和每个片状电容器20之间的距离缩短，并且环路电感减小。 此外，芯片电容器20被容纳在具有大厚​​度的芯基板30中。 因此，印刷电路板的厚度不会变大。