公开(公告)号：JP2001035178A

公开(公告)日：2001-02-09

申请号：JP2000171999

申请日：2000-06-05

Applicant: ST MICROELECTRONICS SRL ,  MITSUBISHI ELECTRIC CORP

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  OBA ATSUSHI ,  CARRERA MARCELLO

IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10 ,  G11C11/56 ,  G11C16/02 ,  G11C16/08 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

Abstract: PROBLEM TO BE SOLVED: To transfer high voltage to a load or a circuit of a post stage by reducing current loss during switching operation when an input signal of low voltage exists in a switch circuit of a CMOS type for transferring high voltage. SOLUTION: This circuit is provided with first, second and third reference potential lines 50, 54, 55, a control input 41a receiving a control signal being swithable between the first and the third potentials, and a drive inverter stage 44 having an input node and an output node 70, a feedback inverter stage 43 is provided with a first upper part transistor and a lower part transistor 51, 53, a control terminal of the first upper part transistor is connected to an output node, a control terminal of the first lower part transistor is connected to a control input, an intermediate node 58 of the feedback inverter stage is connected to an input node, start elements 80, 71 facilitate switching of the intermediate node from a third potential to a second potential.

公开(公告)号：JP2001028608A

公开(公告)日：2001-01-30

申请号：JP2000160376

申请日：2000-05-30

Applicant: ST MICROELECTRONICS SRL

Inventor： DELLA TORRE LUIGI ,  RONCHI MARCO ,  VITALI ANDREA

IPC: H03D1/00 ,  H04L7/00 ,  H04L27/06 ,  H04N5/455

Abstract: PROBLEM TO BE SOLVED: To restore the frequency and phase of a carrier by generating a first carrier which is not correlated to an input signal, to be modulated, to multiply the first carrier by the input signal, which should be modulated, and removing radiation of undesirable spectrum by plural filters arranged at the up/down stream of a multiplier. SOLUTION: A signal reaching from a tuner 11 is sampled by an analog/ digital converter 12 and supplied to a block 10, next. The block 10 includes an input filter 1, a low-pass filter 2 and a multiplier 3 for removing radiation of undesirable spectrum. In the block 10, the multiplier 3 multiplies a signal outputted from the filter 1 by a carrier given by a carrier generator 13. A digital demodulator includes a means for detecting phase shift between the frequency of an input signal (x), which is given from the converter 12 and supplied to the filter 1, and a local carrier in addition.

公开(公告)号：JP2001016322A

公开(公告)日：2001-01-19

申请号：JP2000125357

申请日：2000-04-26

Applicant: ST MICROELECTRONICS SRL

Inventor： NICOLLINI GERMANO ,  PERNICI SERGIO

IPC: H04R3/00 ,  H03G3/34 ,  H04M1/00 ,  H04M1/60 ,  H04M1/72

Abstract: PROBLEM TO BE SOLVED: To provide a final-stage amplifier and an electroacoustic, transducer whose one terminal is connected to a ground terminal to a reception section of a telephone set and to eliminate a filtering element without causing disturbances. SOLUTION: This reception section is provided with a final-stage amplifier 12, an electroacoustic transducer 13 with a 1st terminal connected to the ground point of the circuit of the reception section, a switch on/off control unit, a reference voltage power supply 30, a switch 21 that selects a 1st position or a 2nd position and selectively connects the 2nd terminal of the electroacoustic transducer 13 to a reference voltage terminal REF or an output terminal OUT of the final-stage amplifier 12 via a capacitor Cest, and a control means 20 that activates or inactivated the final stage amplifier 12 and the reference voltage source 30, in response to a signal PD of the switch on/off control unit and operates the switch 21 according to a prescribed time program. This reception section operates with immunity to disturbances similar to a completely balanced structure, even when the electroacoustic transducer 13 is not connected between two balanced output terminals.

公开(公告)号：JP2000357796A

公开(公告)日：2000-12-26

申请号：JP2000150927

申请日：2000-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI ANTONIO ,  GRIMALDI ANTONIO ,  FERLA GIUSEPPE

IPC: H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To resist the high operating voltage whereto a device is subjected, by providing a voltage divider wherein an edge termination includes a plurality of MOS transistors connected in series with each other, and by providing connectively the edge termination between the terminals of a power constituting element whose drivings are impossible. SOLUTION: A device 1 comprises a MOSFET power transistor 21 connected with an edge termination 100. The power transistor 21 is connected in parallel with the series circuit comprising a diode 41 plus the series circuit comprising PMOS parasitic transistors 31, 32, 33, 34. To allow the current flowing from a source terminal S4 of the fourth PMOS parasitic transistor 34 to a source S of the MOSFET power transistor 21, these PMOS parasitic transistors 31-34 are switched on respectively when their respective sources overcome the respective threshold voltages of the PMOS parasitic transistors 31-34. Therefore, there is obtained a limit to the high operating voltage whereto the device 1 is subjected.

公开(公告)号：JP2000332139A

公开(公告)日：2000-11-30

申请号：JP37172599

申请日：1999-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： LOCATI VANDA ,  NORIS CHIORDA GIANLUIGI ,  BESANA LUCA

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell which improves the length control of a cell channel area and has a reduced size by forming the injection area of the bit line, etc., of a virtual grounded memory cell in a salicide area by injecting a dopant into the area at a low concentration. SOLUTION: A method for manufacturing an electronic memory cell device includes a step of forming a plurality of continuous strips which are separated from each other by a plurality of parallel openings 8 by forming the gate areas 4 of a memory cell, a step of forming second-conductivity bit lines 9 in the openings 8 by injecting a dopant, and a step of forming spacers 10 on the side walls of the gate areas 4. The method also includes a step of vapor-depositing first layers 11 of a transition metal in the openings 8, and a step of forming silicon compound layers 12 on the bit lines 9 by causing the transition metal layers 11 to react to a semiconductor substrate by performing heat treatment on the layers 11.

公开(公告)号：JP2000251480A

公开(公告)日：2000-09-14

申请号：JP2000049429

申请日：2000-02-25

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

IPC: G11C16/02 ,  G11C11/56

Abstract: PROBLEM TO BE SOLVED: To provide a read-out method and a memory by which a multi-level cell can be read out quickly and reliably. SOLUTION: Reading circuits 30, 31, 32 comparing the current flowing in a cell containing plural reference currents are not same mutually, but the compared current is made different and amplified. Especially, the reading circuit 32 relating to the minimum reference current IR3 amplifies a cell current of other reading circuits 30, 31 or more until reaching respective reference current 33c. Thereby, current dynamics is increased, read-out voltage can be kept at a low level. Thus, an intrinsic characteristic of the minimum reference current IR3 is near a characteristic of a memory cell distribution IM3 or in the characteristic, possibility of discrimination among different logic levels is reduced.

公开(公告)号：JP2000236033A

公开(公告)日：2000-08-29

申请号：JP2000031789

申请日：2000-02-09

Applicant: ST MICROELECTRONICS SRL

Inventor： PIERAMEDEO BOCCINI

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/02 ,  H01L23/495 ,  H01L23/498

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can be easily and economically manufactured and can provide superior versatility for a lead frame, and also to provide a method for manufacturing the semiconductor device. SOLUTION: This semiconductor device includes a flat insulating film 12, a semiconductor chip 13 which forms a drive part of the device, is fixed to a supporting member and has a metallized region 17 on one of its broader surfaces, an electrically interconnecting member 20 disposed between the metallized region of the chip 13 and a connection end of a terminal conductor and having a strip of anisotropic conductive material, and hermetically sealing means for surrounding the chip 13, which is the connection end of the terminal conductor and the electrically interconnecting member. The electrically interconnecting member has conductive tracks 18 made on the insulating film.

公开(公告)号：JP2000233400A

公开(公告)日：2000-08-29

申请号：JP2000031704

申请日：2000-02-09

Applicant: ST MICROELECTRONICS SRL

Inventor： FERRARI PAOLO ,  VIGNA BENEDETTO ,  MONTANINI PIETRO ,  LORA CASTOLDI ,  MARCO FERUREA

IPC: B81B3/00 ,  G01P15/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an microminiature integrated structural body capable of removing or reducing residual stress considerably. SOLUTION: A sacrifice region 21 is formed on a substrate 20 of a semiconductor material, an epitaxial layer 25 grows, then a stress release groove 31 is formed by surrounding a region 33 of the epitaxial layer 25 in which an electromechanical microminiature integrated structural body is formed, and then a wafer 28 is heat-treated to release residual stress. In succession, a seal region of a dielectric material is filled in the stress release groove 31 to form an integrated microminiature constituting element. Finally, a groove defining the ultra-micro structural body is formed on an inner side of a region surrounded by the seal region, then the sacrifice region is removed, and the microminiature integrated structual body without residual stress is formed.

公开(公告)号：JP2000208721A

公开(公告)日：2000-07-28

申请号：JP2000006540

申请日：2000-01-14

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  PAOLA ZULIANI ,  LORENZO FURATIN

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/00 ,  H01L23/58

Abstract: PROBLEM TO BE SOLVED: To prevent a COB(chip outline band) structure body from acting as an obstacle element, when the COB structure body is operated in an electromagnetic field. SOLUTION: This chip outline band (COB) structure body is used in a integrated circuit, which is integrated in a semiconductor chip having a first conductivity-type semiconductor substrate 1, and the substrate is biased to a common reference potential (GND) of the integrated circuit. The chip outline band structure body is provided with a substantially annular region 3 formed in the substrate 1 along its periphery, and at least annular conducting regions 40, 60 which is superposed on the annular region 3 and is in contact with the annular region 3. The region 3 is electrically connected with a point of the common reference potential (GND).

公开(公告)号：JP2000183317A

公开(公告)日：2000-06-30

申请号：JP35098199

申请日：1999-12-10

Applicant: ST MICROELECTRONICS SRL

Inventor： BARLOCCHI GABRIELE ,  VILLA FLAVIO

IPC: H01L21/301 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To eliminate a crystallographic failure which exists in an epitaxial layer by eliminating a surface region of a first trench side wall locating at a lower position than a first protecting region after graving and punching. SOLUTION: A mask 9 as an anti-oxidizing material is formed on a wafer 1 by defining a first protecting region 7 which covers a first part 8' of the wafer 1. After mutually separating a second part 8" which is not covered by the mask 9 from the first part 8', the second part 8" is graved and punched and a first a first trench 10 which exists by extending between the first part 8' is formed. And after each first trench 10 is defined by a side wall 10a and a bottom wall 10h, a surface region of the side wall 10a of the first trench 10 which locates at a lower position than the first protecting region 7 is eliminated. By the means a crystallographic failure which exists in an epitaxial layer can be eliminated.