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211.发明公开
公开(公告)号：EP2080822A1
公开(公告)日：2009-07-22
申请号：EP06823030.9
申请日：2006-11-06
Applicant: C. Uyemura & Co., Ltd.
Inventor： YAMAMOTO, Hisamitsu
CPC classification number: C23C18/44 , C23C18/1653 , C23C18/2086 , C23C18/30 , C25D5/02 , C25D5/56 , H05K1/0346 , H05K3/181 , H05K3/422 , H05K3/427 , H05K2201/0344 , H05K2203/124
Abstract: A surface of an object to be plated is subjected to a treatment for palladium catalyst impartation to impart a palladium catalyst to the surface of an insulating part thereof. A palladium conductor layer is formed on the insulating part from a solution for palladium conductor layer formation which contains a palladium compound, an amine compound, and a reducing agent. On the palladium conductor layer is then directly formed a copper deposit by electroplating. Thus, the work is converted to a conductor with the solution for palladium conductor layer formation, which is neutral, without using an electroless copper plating solution which is highly alkaline. Consequently, the polyimide is prevented from being attacked and no adverse influence is exerted on adhesion. By adding an azole compound to the solution for palladium conductor layer formation, a palladium conductor layer is prevented from depositing on copper. Thus, the reliability of connection between the copper part present on a substrate and the copper deposit formed by electroplating is significantly high.
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212.发明公开
公开(公告)号：EP1923489A3
公开(公告)日：2009-05-27
申请号：EP08152454.8
申请日：1999-09-14
Applicant: Ibiden Co., Ltd.
Inventor： En, Honchin , Nakai, Tohru , Oki, Takeo , Hirose, Naohiro , Noda, Kouta
CPC classification number: H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
Abstract: A multilayer printed circuit board (5010) comprises a core board (5030) and, as constructed on both sides thereof, a buildup wiring layer obtainable by building up an interlayer resin insulating layer (5050, 5150) and a conductor layer (5058, 5158) alternately with said conductor layers (5058, 5158) being interconnected by via holes (5160). The via holes (5060, 5160) are formed immediately over plated-through holes (5036) in the manner of plugging the through holes (5016) in the core board (5030). In a process for manufacturing the multilayer printed circuit board (5010), the through holes (5016) are pierced by laser light to be not larger than 200 µm in diameter.
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213.发明公开A process for manufacturing a multilayer printed circuit board 审中-公开Verfahren zur Herstellung einer mehrschichtigen Leiterplatte
公开(公告)号：EP1923488A2
公开(公告)日：2008-05-21
申请号：EP08152453.0
申请日：1999-09-14
Applicant: Ibiden Co., Ltd.
Inventor： En, Honchin , Nakai, Tohru , Oki, Takeo , Hirose, Naohiro , Noda, Kouta
IPC: C25D5/18
CPC classification number: H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
Abstract: A process for manufacturing a multilayer printed circuit board comprises a step for providing openings in an interlayer insulating layer (4002), and a step for filling up the openings with a plating metal to construct via holes (4007) and, at the same time, build up an upper-layer conductor layer (4005). The electroplating is performed using an aqueous solution containing a metal ion and 0.1 to 1.5 mmol/L of at least one additive selected from the group consisting of thioureas, cyanides and polyalkylene oxides as a plating solution.
Abstract translation: 一种制造多层印刷电路板的方法包括在层间绝缘层（4002）中提供开口的步骤，以及用电镀金属填充开口以构造通孔（4007）的步骤，同时， 建立上层导体层（4005）。 使用含有金属离子的水溶液和0.1〜1.5mmol / L的选自硫脲，氰化物和聚环氧烷作为电镀液的至少一种添加剂进行电镀。
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214.发明授权IMPROVED METHOD FOR FORMING CONDUCTIVE TRACES AND PRINTED CIRCUITS MADE THEREBY 有权改进的方法生产传导轨道，这样生产印制电路板
公开(公告)号：EP1099361B1
公开(公告)日：2007-02-28
申请号：EP99930884.4
申请日：1999-07-09
Applicant: Oak-Mitsui, Inc.
Inventor： CARBIN, Derek , HERRICK, Wendy, A.
CPC classification number: H05K3/025 , H05K3/108 , H05K3/384 , H05K3/4652 , H05K2201/0317 , H05K2201/0344 , H05K2201/0355 , H05K2201/10477 , H05K2203/0152 , H05K2203/0307 , H05K2203/0723 , H05K2203/0726 , Y10T29/49155
Abstract: A method of forming circuit lines on a substrate by applying a roughened conductive metal layer using a copper foil carrier. The copper foil is etched away, leaving the roughened conductive metal embedded in the surface of the substrate. The conductive metal may be treated to remove an oxide layer. A photoresist may also be applied over the treated conductive metal layer to define a fine line circuit pattern. The photoresist defining the fine line circuit pattern is then removed to expose trenches in accordance with the desired circuit pattern. Copper is applied into the trenches over the exposed conductive metal, and the remaining photoresist, and conductive metal underlying the remaining photoresist, is removed to finish the fine line circuit pattern.
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公开(公告)号：EP1117283B1
公开(公告)日：2006-05-10
申请号：EP99943326.1
申请日：1999-09-14
Applicant: IBIDEN CO., LTD.
Inventor： EN, Honchin , NAKAI, Tohru , OKI, Takeo , HIROSE, Naohiro , NODA, Kouta
CPC classification number: H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
Abstract: A method for manufacturing a printed wiring board having a high-density wiring and a highly-reliable connection between conductor layers even if the annealing process is omitted because a conductor circuit made of an electroplating layer excellent in crystallinity and uniform electrodepositability and formed on a base sheet and a via hole are provided. The method comprising forming an interlayer resin insulating layer on a conductor wiring forming board, making an opening for making a via hole in the interlayer resin insulating layer, forming an electroless plating layer (1008) on the interlayer resin insulating layer, applying a resist film (1003) to the layer (1008), forming an electroplating film thereon, removing the resist film, and removing the electroless plating layer by etching so as to form a conductor wiring and a via hole characterized in that the electroless plating layer (1008) serves as a cathode, the plating metal serves as an anode, and electroplating is performed intermittently while maintaining the voltage between the anode and cathode at a constant value.
Abstract translation: 即使省略退火处理，由于由结晶性和电沉积性均匀性优异的电镀层构成的导体电路形成于基体上，因此即使省略退火处理，也能够提供具有高密度布线和导体层间的可靠性高的连接的印刷布线板的制造方法 薄片和通孔。 该方法包括：在导体布线形成板上形成层间树脂绝缘层，在层间树脂绝缘层上形成用于形成通孔的开口，在层间树脂绝缘层上形成化学镀层（1008），将抗蚀剂膜 （1008），在其上形成电镀膜，去除抗蚀剂膜，并且通过蚀刻除去化学镀层，从而形成导体布线和通孔，其特征在于，无电镀层（1008） 用作阴极，电镀金属用作阳极，并且在将阳极和阴极之间的电压保持在恒定值的同时间歇地执行电镀。
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Patent Agency Ranking216.发明授权
公开(公告)号：EP0837623B1
公开(公告)日：2004-08-18
申请号：EP97307983.3
申请日：1997-10-09
Applicant: MACDERMID INCORPORATED
Inventor： Kukanskis, Peter , Larson, Gary B. , Bengston, Jon , Schweikher, William
CPC classification number: H05K1/167 , H01C17/065 , H01C17/18 , H05K3/064 , H05K3/184 , H05K3/381 , H05K2201/0344 , H05K2203/025 , H05K2203/0315 , H05K2203/0796 , H05K2203/095 , H05K2203/1453
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公开(公告)号：EP1166353A4
公开(公告)日：2003-06-04
申请号：EP99964034
申请日：1999-12-01
Applicant: GA TEK INC
Inventor： BERGSTRESSER TAD , POUTASSE CHARLES A
IPC: B32B15/08 , B32B15/088 , H05K1/03 , H05K3/18 , H05K3/24 , H05K3/38 , H05K3/46 , H01L23/053 , H01L23/10 , H01L23/12 , H01L23/34
CPC classification number: H05K3/4655 , H01L2924/0002 , H05K3/181 , H05K3/386 , H05K3/387 , H05K3/388 , H05K3/4652 , H05K2201/0195 , H05K2201/0344 , Y10T428/12542 , Y10T428/12556 , Y10T428/1291 , Y10T428/12917 , Y10T428/24917 , Y10T428/28 , Y10T428/31681 , H01L2924/00
Abstract: A laminate for use as a surface laminate in a multi-layer printed circuit board. The laminate is comprised of a film substrate (12) formed of a first polymeric material. At least one layer of a flash material (14) is applied to a first side of the film substrate. At least one layer of copper (16) is disposed on the layer of flash material. An adhesive layer (18) formed of a second polymer material has a first surface that is attached to a second side of the film substrate.
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218.发明授权
公开(公告)号：EP0747507B1
公开(公告)日：2001-02-14
申请号：EP95932961.6
申请日：1995-10-03
Applicant: IBIDEN CO., LTD.
Inventor： YUAN, Benzhen , ASAI, Motoo
CPC classification number: H05K3/244 , C23C18/1651 , C23C18/166 , C23C18/1834 , H05K3/062 , H05K3/108 , H05K3/181 , H05K3/184 , H05K2201/0344 , H05K2203/0392 , H05K2203/072
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公开(公告)号：EP0732040B1
公开(公告)日：1998-02-11
申请号：EP95904600.4
申请日：1994-12-02
Applicant: MACDERMID INCORPORATED
Inventor： Knopp, John Frederick David
IPC: H05K3/42
CPC classification number: H05K3/428 , H05K2201/0344 , H05K2203/0565 , H05K2203/0723
Abstract: A method of making a plate through hole printed circuit board, comprises the steps of: a) forming conductive circuit elements (10) on two opposed faces of a paper phenolic containing substrate (11); b) coating the substrate and circuit elements with a de-sensitising material (12); c) forming holes (13) through the substrate, each hole passing through a circuit element on each of the opposed faces of the board; d) treating the board to render the substrate exposed in the holes receptive to the action of a metallic plating solution; e) removing the de-sensitising material; f) printing an acid-resist mask (14) on to both faces of the board, the mask leaving exposed only a small area of the board surrounding each hole therethrough; and g) treating the board with an electroless nickel-plating solution to deposit nickel (15) in the holes to the desired thickness to provide an electrical connection through each hole between two opposed conductive circuit elements.
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公开(公告)号：EP0645074B1
公开(公告)日：1998-01-28
申请号：EP93913258.5
申请日：1993-06-01
Applicant: MACDERMID INCORPORATED
Inventor： Knopp, John Frederick David
IPC: H05K3/42
CPC classification number: H05K3/428 , H05K2201/0344 , H05K2203/0565 , H05K2203/0723 , H05K2203/1383
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