公开(公告)号：EP1631131A2

公开(公告)日：2006-03-01

申请号：EP05018487.8

申请日：2005-08-25

Applicant: HIROSE ELECTRIC CO., LTD.

Inventor： Matsuo, Tsutomu c/o Hirose Electric Co., Ltd. ,  Nagata, Masakazu c/o Hirose Electric Co., Ltd.

IPC: H05K1/03

CPC classification number: H01P3/088 ,  H05K1/024 ,  H05K2201/0715 ,  H05K2201/09045 ,  H05K2201/2036

Abstract: A transmission circuit board structure comprises at least one signal layer formed by a plurality of signal lines (20) arranged side by side, at least one ground layer formed of a ground plate (30) and provided in parallel to the signal layer, and a support member (10) made of a dielectric material, formed integrally with the signal lines to support the signal lines. The support member (10) has at least one connection member (12), which abuts against the ground plate (30) at a position where the insulation layer made by an air space is produced between the signal lines (20) and the ground plate (30).

Abstract translation: 传输电路板结构包括由并排布置的多个信号线（20）形成的至少一个信号层，由接地板（30）形成并且与信号层平行设置的至少一个接地层，以及 由介电材料制成的支撑构件（10），与信号线整体形成以支撑信号线。 支撑构件（10）具有至少一个连接构件（12），其在由信号线（20）和接地板（20）之间产生由空气空间制成的绝缘层的位置处抵靠接地板（30） （30）。

公开(公告)号：EP0915641B1

公开(公告)日：2006-02-08

申请号：EP98120662.6

申请日：1998-11-04

Applicant: NEC CORPORATION

Inventor： Tamura, Koetsu ,  Matsuzawa, Hajime

IPC: H05K1/18 ,  H05K3/34

CPC classification number: H05K1/183 ,  H05K1/0284 ,  H05K1/117 ,  H05K3/1225 ,  H05K3/3405 ,  H05K3/3484 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K2201/10734

公开(公告)号：EP1544916A1

公开(公告)日：2005-06-22

申请号：EP04029916.6

申请日：2004-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song, Hoon ,  Shim, Dong-sik

IPC: H01L23/485 ,  H01L29/06 ,  H01L21/60 ,  H05K3/34 ,  H01L23/13 ,  H05K1/11

CPC classification number: H01L24/13 ,  H01L23/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/381 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Aflip-chip package for implementing a fine solder ball, and a flip-chip packaging method using the same. The flip-chip package includes a first wafer (100) having a first electrode and a first under bump metal (111,112) (UBM) formed on the first electrode and electrically connected to the first electrode; and second wafer (200) opposing the first wafer and having a second electrode located in a position corresponding to the first electrode, and a second UBM (211,212) formed of the second electrode and electrically connected to the second electrode. The first wafer (100) has a depression formed on one or more areas adjacent to the first UBM (111,112), which depression partly receives a solder ball (133a,134a) that connects the first (111,112) and the second UBMs (211,212) upon flip-chip bonding of the first (100) and second (200) wafers. Since the UBM is formed as an embossing pattern, a fine solder ball can be implemented. Additionally, the reliability of the package can be improved.

Abstract translation: 用于实现精细焊球的微片芯片封装以及使用其的倒装芯片封装方法。 倒装芯片封装包括具有形成在第一电极上并电连接到第一电极的第一电极和第一下凸块金属（111,112）（UBM）的第一晶片（100） 和与第一晶片相对并且具有位于对应于第一电极的位置的第二电极的第二晶片（200）和由第二电极形成并电连接到第二电极的第二UBM（211,212）。 第一晶片（100）具有形成在与第一UBM（111,112）相邻的一个或多个区域上的凹陷，该凹陷部分地接收连接第一（111,112）和第二UBM（211,212）的焊球（133a，134a） 在第一（100）和第二（200）晶片的倒装芯片接合时。 由于UBM形成为压花图案，因此可以实现精细的焊球。 此外，可以提高包装的可靠性。

公开(公告)号：EP1215087A3

公开(公告)日：2003-11-26

申请号：EP01310309.8

申请日：2001-12-10

Applicant: Sumitomo Wiring Systems, Ltd.

Inventor： Kato, Shinshu, c/o Sumitomo Wiring Systems, Ltd. ,  Yuasa, Eriko, c/o Sumitomo Wiring Systems, Ltd.

IPC: B60R16/02

CPC classification number: H05K7/026 ,  H01R9/226 ,  H05K1/0256 ,  H05K1/0298 ,  H05K3/107 ,  H05K3/202 ,  H05K2201/09036 ,  H05K2201/09045 ,  Y10S439/949

Abstract: An electrical connection box for a vehicle has a low-voltage bus bar (10) and a high voltage bus bar (11), received in groove structures (12b; 12d) of a first insulation plate (12). Each groove structure is defined by a base wall surface on which the bus bar is disposed and a pair of opposed upstanding side wall surfaces. The first insulation plate has a downward recess (12c) or through-hole between the groove structures. A second insulation plate (22) superimposed on the first plate (12) has a downward projection (22a) received in the recess (12c) or through-hole and extending to a lower end which is below the base wall surfaces of the groove structures. The structure inhibits leak currents between the bus bars.

公开(公告)号：EP1247343A1

公开(公告)日：2002-10-09

申请号：EP00983625.5

申请日：2000-12-01

Applicant: FRAMATOME CONNECTORS INTERNATIONAL

Inventor： GREK, Joachim

IPC: H03L1/00

CPC classification number: H05K1/147 ,  H01R12/716 ,  H05K1/0284 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3447 ,  H05K2201/049 ,  H05K2201/09045 ,  H05K2201/10189

Abstract: A slanted connector and a method for mounting the same, having first connector means (20) extended in a first direction and second connector means (29a-c) extended in a slanted direction in relation to the first connector means (20).According to the invention the slanted connector comprises a first part (2) comprising the first connector means (20) and a second part (21a-e) comprising the second connector means (29a-c). The second part (21a-e) is connectable to the first connector means (20) and has a bent form in order to engage the first connector means (20) in a first direction and provide the second connector means (29a-c) protruding in at least one second direction slanted to the first direction, the second part (21a-e) having a circuit pattern to connect the first connector means (20) to the second connector means (29a-c).

公开(公告)号：EP1209959A2

公开(公告)日：2002-05-29

申请号：EP01126948.7

申请日：2001-11-13

Applicant: Matsushita Electric Works, Ltd.

Inventor： Uchinono, Yoshiyuki, c/o Matsushita Electric Works ,  Sawada, Kazuo, c/o Matsushita Electric Works ,  Masaki, Yasufumi, c/o Matsushita Electric Works ,  Muto, Masahide, c/o Matsushita Electric Works

IPC: H05K3/46

CPC classification number: H05K1/183 ,  B29L2031/3493 ,  H05K1/0284 ,  H05K1/119 ,  H05K3/027 ,  H05K3/403 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/09645 ,  Y10T29/49155

Abstract: A molded interconnect device (MID) having a multilayer circuit of a reduced thickness, in which a layer-to-layer connection(s) is formed with high reliability, is provided as a multilayer circuit board. The multilayer circuit board comprises a substrate having a first surface and a second surface extending from an end of the first surface at a required angle relative to the first surface, and the multilayer circuit formed on the first surface and composed of a plurality of circuit layers. Each of the circuit layers is provided with a conductive layer having a required circuit pattern and an insulation layer formed on the conductive layer by film formation. The layer-to-layer connection of the multilayer circuit is made through a second conductive layer formed on the second surface of the substrate.

Abstract translation: 提供具有减小厚度的多层电路的模制互连装置（MID），其中以高可靠性形成层间连接（一个或多个）作为多层电路板。 多层电路板包括具有第一表面和从第一表面的端部以相对于第一表面的所需角度延伸的第二表面的基板，并且多层电路形成在第一表面上并且由多个电路层 。 每个电路层设置有具有所需电路图案的导电层和通过成膜在导电层上形成的绝缘层。 多层电路的层间连接通过形成在衬底的第二表面上的第二导电层来形成。

公开(公告)号：EP1187259A2

公开(公告)日：2002-03-13

申请号：EP01307481.0

申请日：2001-09-03

Applicant: Sumitomo Wiring Systems, Ltd.

Inventor： Yuasa, Eriko ,  Kato, Shinshu

IPC: H01R9/24

CPC classification number: H05K1/0256 ,  H01H2085/208 ,  H01R9/2458 ,  H01R2201/26 ,  H05K3/202 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09045 ,  Y10S439/949

Abstract: An electrical connection box for use in a vehicle has bus bars (10, 11) in a casing with upstanding connection tabs (10a, 11a) which are alongside and spaced from each other. Insulation resin embeds the tabs while leaving exposed projecting portions. A connector (20) attached to the casing has a housing (21) containing terminals (7, 8) respectively engaged with the projecting portions of the tabs. The resin material provides a recess (15) located between the tabs (10a, 11a) and the housing of said connector (20) has a partition wall (22) of insulating material which lies between the terminals (7, 8) and extends into the recess (15), to prevent leak current between the terminals.

Abstract translation: 一种用于车辆中的电连接盒，具有位于壳体中的汇流条（10,11），该汇流条具有直立的连接片（10a，11a），所述连接片沿着彼此并且彼此间隔开。 绝缘树脂嵌入接片，同时留下暴露的突出部分。 连接到壳体的连接器（20）具有包含分别与突片的突出部分接合的端子（7,8）的壳体（21）。 树脂材料提供位于凸片（10a，11a）之间的凹槽（15），并且所述连接器（20）的壳体具有位于端子（7,8）之间并延伸到绝缘材料的隔离材料的隔壁（22） （15），以防止端子之间的泄漏电流。

公开(公告)号：EP1155603A1

公开(公告)日：2001-11-21

申请号：EP00900531.5

申请日：2000-01-06

Applicant: Novatec S.A.

Inventor： BOURRIERES, Francis ,  KAISER, Clément

IPC: H05K3/34 ,  H05K3/36

CPC classification number: H05K3/34 ,  H05K1/0284 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3478 ,  H05K3/3484 ,  H05K3/368 ,  H05K2201/09045 ,  H05K2201/10477 ,  H05K2203/041 ,  H05K2203/082 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: The invention concerns a method for producing electronic modules with ball connector (7) or integrated preforms capable of being soldered on a printed circuit (3) and a device for implementing said method. The invention concerns a method for producing electronic modules in the form of ball housings combining a ball grid array (7) or geometrically identical preforms for interconnecting or shielding and surface-mounted components (2) on the same surface of a substrate (1), thereby enabling said module to be directly connectable by soldering on a printed circuit (3). The balls (7) and the components (2) are transferred in one single step onto the substrate (1) by means of a gripping device adapted to the topography of the module to be produced.

公开(公告)号：EP0792518A1

公开(公告)日：1997-09-03

申请号：EP95940644.0

申请日：1995-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： AKRAM, Salman ,  FARNWORTH, Warren, M. ,  WOOD, Alan, G.

IPC: G01R1 ,  B81C1 ,  H01L21 ,  H05K1 ,  H05K3

CPC classification number: G01R1/06738 ,  G01R1/07314 ,  H01L2224/13019 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10T29/49155 ,  Y10T29/49453

Abstract: A method for forming a self-limiting, silicon based interconnect for making temporary electrical contact with bond pads on a semiconductor die is provided. The interconnect includes a silicon substrate having an array of contact members adapted to contact the bond pads on the die for test purposes (e.g., burn-in testing). The interconnect is fabricated by: forming the contact members on the substrate; forming a conductive layer on the tip of the contact members; and then forming conductive traces to the conductive layer. The conductive layer is formed by depositing a silicon containing layer (e.g., polysilicon, amorphous silicon) and a metal layer (e.g., titanium, tungsten, platinum) on the substrate and contact members. These layers are reacted to form a silicide. The unreacted metal and silicon containing layer are then etched selective to the conductive layer which remains on the tip of the contact members. Conductive traces are then formed in contact with the conductive layer using a suitable metallization process. Bond wires are attached to the conductive traces and may be attached to external test circuitry. Alternately, another conductive path such as external contacts (e.g., slide contacts) may provide a conductive path between the conductive traces and external circuitry. The conductive layer, conductive traces and bond wires provide a low resistivity conductive path from the tips of the contact members to external test circuitry.

公开(公告)号：EP0773584A2

公开(公告)日：1997-05-14

申请号：EP96308093.2

申请日：1996-11-07

Applicant: FUJITSU LIMITED

Inventor： Yoneda, Yoshiyuki ,  Tsuji, Kazuto ,  Orimo, Seiichi ,  Sakoda, Hideharu ,  Nomoto, Ryuji ,  Onodera, Masanori ,  Kasai, Junichi

IPC: H01L23/31

CPC classification number: H01L21/4832 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67138 ,  H01L21/6833 ,  H01L23/3107 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/7865 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85664 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/3011 ,  H05K1/181 ,  H05K3/303 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/09045 ,  H05K2201/10727 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A device includes a chip (111), and a resin package (112, 151, 314) sealing the chip, the resin package having resin projections (117, 154, 318) located on a mount-side surface of the resin package. Metallic films (113, 155, 315) are respectively provided to the resin projections. Connecting parts (118, 101, 163, 245, 313, 341, 342) electrically connect electrode pads of the chip and the metallic films.