公开(公告)号：US09338897B2

公开(公告)日：2016-05-10

申请号：US14133238

申请日：2013-12-18

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Yuma Otsuka ,  Kazunori Fukunaga ,  Atsushi Uchida ,  Kouhei Yoshimura

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/40 ,  H05K3/38 ,  H05K3/10 ,  H05K3/14 ,  H05K3/16 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K3/4007 ,  H05K1/0306 ,  H05K3/108 ,  H05K3/146 ,  H05K3/16 ,  H05K3/244 ,  H05K3/388 ,  H05K3/403 ,  H05K3/4617 ,  H05K2201/09181 ,  H05K2201/09545 ,  H05K2201/09845 ,  H05K2203/1105 ,  H05K2203/1338 ,  H05K2203/1394 ,  H05K2203/1461

Abstract: A ceramic substrate is provided that includes a ceramic substrate main body including a principal surface, a connecting terminal portion disposed on the principal surface of the ceramic substrate main body that is capable of being connected to another component via solder, the connecting terminal portion including a copper layer and a coating metal layer covering a surface of the copper layer; a contact layer of titanium or chromium disposed between the ceramic substrate main body and the connecting terminal portion; and an intermediate layer disposed between the copper layer of the connecting terminal portion and the contact layer, the intermediate layer including one of a titanium-tungsten alloy, a nickel-chromium alloy, tungsten, palladium, and molybdenum. The contact layer and the intermediate layer are set back from a side surface of the copper layer in a substrate plane direction.

Abstract translation: 提供一种陶瓷基板，其包括：陶瓷基板主体，其包括主表面;连接端子部，其设置在能够通过焊料与另一部件连接的陶瓷基板主体的主面上;连接端子部， 铜层和覆盖铜层表面的涂层金属层; 设置在陶瓷基板主体和连接端子部之间的钛或铬的接触层; 以及设置在连接端子部分的铜层和接触层之间的中间层，中间层包括钛 - 钨合金，镍 - 铬合金，钨，钯和钼中的一种。 接触层和中间层在基板平面方向上从铜层的侧表面返回。

公开(公告)号：US20160091991A1

公开(公告)日：2016-03-31

申请号：US14502949

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Aidan N. Zimmerman ,  Bruce E. Berg ,  Gleen Aune ,  Kevin C. Armendariz ,  Ryan P. Brooks

IPC: G06F3/0354 ,  H05K1/11 ,  G06F3/046 ,  H05K1/03 ,  H05K3/40 ,  H05K3/00 ,  H01Q1/24 ,  H05K1/02

CPC classification number: G06F3/03545 ,  G06F3/044 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/3025 ,  H01Q1/243 ,  H05K1/0274 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/284 ,  H05K3/4038 ,  H05K2201/09027 ,  H05K2201/09545

Abstract: An electronic device may have printed circuits to which electrical components are mounted. Plastic may be molded over a printed circuit. Vias may be formed in the printed circuit that connect metal traces on the surface of the molded plastic to metal traces on the printed circuit. The vias may be formed by drilling or by covering the metal traces on the printed circuit with mold pins in a molding tool during plastic molding operations. Plated metal traces or other metal traces may extend onto the interior surface of via holes. Vias may also be filled with conductive material such as solder or conductive adhesive. Metal members that are soldered or otherwise connected to printed circuit traces may be used in coupling surface metal traces to printed circuit traces. Antenna structure, shielding structures, and electrodes for a stylus may be formed using the metal traces on the molded plastic.

Abstract translation: 电子设备可以具有安装电气部件的印刷电路。 塑料可以在印刷电路上模制。 可以在印刷电路中形成通孔，其将模制塑料表面上的金属迹线连接到印刷电路上的金属迹线。 可以通过在塑料模制操作期间通过钻孔或通过在模制工具中的模具销覆盖印刷电路上的金属迹线来形成通孔。 镀金属痕迹或其他金属迹线可延伸到通孔的内表面。 通孔也可以填充导电材料，例如焊料或导电粘合剂。 焊接或以其他方式连接到印刷电路迹线的金属构件可用于将表面金属迹线耦合到印刷电路迹线。 用于触针的天线结构，屏蔽结构和电极可以使用模制塑料上的金属迹线形成。

公开(公告)号：US20160050769A1

公开(公告)日：2016-02-18

申请号：US14778677

申请日：2014-03-25

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Nobuyuki YOSHIDA

IPC: H05K3/42 ,  C25D7/12 ,  C25D5/34 ,  C25D5/48 ,  H05K1/02 ,  C23C18/16 ,  H05K3/06 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  C25D3/38 ,  C25D5/10

CPC classification number: H05K3/421 ,  C23C18/1653 ,  C23C18/405 ,  C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  C25D7/123 ,  H05K1/0298 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/115 ,  H05K3/06 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  H05K2203/1423

Abstract: To provide a method for manufacturing a multilayer wiring substrate, in which an insulating layer and a metal foil provided thereon are integrally laminated on an inner layer material having a wiring formed thereon, in which a hole for via hole is formed in the metal foil and the insulating layer, and in which the hole for via hole is filled with an electrolytic filled plating layer after a base electroless plating layer is formed, the method being featured in that, after the base electroless plating layer is formed, first, an electrolysis filled plating layer is formed to the extent that the hole for via hole is not completely filled, and then, after the surface of the electrolytic filled plating layer is etched, the hole for via hole is completely filled by an electrolytic filled plating layer.

Abstract translation: 为了提供一种制造多层布线基板的方法，其中设置在其上的绝缘层和金属箔一体层压在其上形成有布线的内层材料上，其中在金属箔中形成有用于通孔的孔， 绝缘层，在形成基底化学镀层之后，通孔的孔填充有电解填充的镀层，其特征在于，在形成基底化学镀层之后，首先，填充电解液 形成电镀层的程度为通孔的孔未完全填充，然后在电解填充镀层的表面被蚀刻后，通孔的孔完全由电解填充镀层填充。

公开(公告)号：US09226396B2

公开(公告)日：2015-12-29

申请号：US13797355

申请日：2013-03-12

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/00 ,  H05K1/16 ,  H05K1/11 ,  H05K7/10 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Abstract translation: 中间体及其制备方法在本文中公开。 在一个实施例中，插入件包括具有第一和第二相对面的表面和多个孔的区域，每个孔从第一表面朝向第二表面沿第一方向延伸，其中氧化铝沿每个孔的壁延伸; 多个导电连接元件，其沿第一方向延伸，主要由铝构成，并通过至少氧化铝彼此电隔离; 第一导电路径，设置在第一表面处，用于与插入件外部的第一部件连接; 以及设置在所述第二表面处用于与所述插入件外部的第二部件连接的第二导电路径，其中所述第一和第二导电路径通过至少一些所述连接元件电连接。

公开(公告)号：US20150366060A1

公开(公告)日：2015-12-17

申请号：US14453952

申请日：2014-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-tzu Tang ,  Ying-Chou Tsai

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/0014 ,  H05K1/116 ,  H05K2201/09118 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49167

Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.

Abstract translation: 提供了一种电路结构，其包括多个导电柱，以及分别形成在导电柱的两个相对端表面上的多个第一和第二导电垫。 每个第一导电焊盘的长度大于第一导电焊盘的宽度，以便沿着宽度减小第一导电焊盘的占用面积并且增加相邻的第一导电焊盘之间的距离，由此增加布线密度和 满足布线需求。

公开(公告)号：US20150351257A1

公开(公告)日：2015-12-03

申请号：US14722246

申请日：2015-05-27

Applicant: KYOCERA Circuit Solutions, Inc.

Inventor： Kohichi OHSUMI ,  Kazuki OKA

IPC: H05K3/42 ,  H05K3/10 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K3/4644 ,  H05K3/108 ,  H05K2201/0347 ,  H05K2201/09336 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09681 ,  H05K2203/025 ,  H05K2203/0723 ,  H05K2203/1476

Abstract: A method for producing a wiring board includes the steps of forming an upper insulating layer on a lower insulating layer having a lower wiring conductor on its upper surface; forming a via-hole in the upper insulating layer; depositing a first base metal layer in the via-hole and on an upper surface of the upper insulating layer; forming a first plating resist layer on the first base metal layer; depositing a first electrolytically plated layer to completely fill at least the via-hole; forming a via conductor, and depositing a second base metal layer; forming a second plating resist layer on the second base metal layer; depositing a second electrolytically plated layer; and forming a wiring pattern.

Abstract translation: 制造布线板的方法包括以下步骤：在其上表面上形成具有下布线导体的下绝缘层上的上绝缘层; 在上绝缘层中形成通孔; 在所述通孔中和所述上绝缘层的上表面上沉积第一基底金属层; 在所述第一基底金属层上形成第一电镀抗蚀剂层; 沉积第一电解镀层以至少完全填充通孔; 形成通孔导体，并沉积第二基底金属层; 在所述第二基底金属层上形成第二电镀抗蚀剂层; 沉积第二电解镀层; 并形成布线图案。

公开(公告)号：US20150319842A1

公开(公告)日：2015-11-05

申请号：US14700373

申请日：2015-04-30

Applicant: IBIDEN CO., LTD.

Inventor： Koji ASANO ,  Naoki KATSUDA

IPC: H05K1/02 ,  H05K3/42 ,  H05K1/11 ,  H05K3/00 ,  H05K3/18

CPC classification number: H05K3/4602 ,  H01L23/12 ,  H01L23/3677 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0206 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/0094 ,  H05K3/181 ,  H05K3/188 ,  H05K3/425 ,  H05K3/427 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A circuit substrate includes an insulating layer, circuit layers including a first layer on first surface side of the insulating layer and a second layer on second surface side of the insulating layer, conductor heat transfer layers including a first transfer layer on the first side of the insulating layer and a second transfer layer on the second side of the insulating layer, through hole electrical conductors filling first through holes penetrating through the insulating layer such that the electrical conductors connect the first and second layers, and a through hole thermal conductor filling a second through hole penetrating through the insulating layer such that the thermal conductor connects the first and second transfer layers. The second hole is positioned between two or more of the first holes and has a shape extending in direction that intersects direction connecting the two or more of the first holes.

Abstract translation: 电路基板包括绝缘层，包括绝缘层的第一表面侧上的第一层和绝缘层的第二表面侧的第二层的电路层，导体传热层，其包括在第一侧上的第一传输层 绝缘层和绝缘层的第二侧上的第二转移层，贯穿绝缘层的第一穿透孔填充的通孔电导体，使得电导体连接第一和第二层，以及填充第二层的通孔热导体 穿透绝缘层的通孔使得热导体连接第一和第二转移层。 第二孔位于两个以上的第一孔之间，具有与连接两个以上的第一孔的方向相交的方向延伸的形状。

公开(公告)号：US20150305157A1

公开(公告)日：2015-10-22

申请号：US14789639

申请日：2015-07-01

Applicant: FUJITSU LIMITED

Inventor： Hideaki YOSHIMURA

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4038 ,  H05K3/425 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.

Abstract translation: 制造布线板的方法包括：在芯基板中形成外通孔; 用绝缘树脂填充外部通孔; 在形成芯连接通孔的部分上在绝缘树脂的表面上形成第一导电层; 形成围绕所述第一导电层的区域; 在形成第一导电层并形成焊盘之后，在芯基板上层叠布线层; 形成直径小于所述外通孔直径的内通孔，穿过所述芯基板和所述布线层以贯穿所述绝缘树脂; 并且在内部通孔的内壁表面上涂覆第一导电膜，其中芯基板和第一导电膜通过第一导电层和焊盘电连接。

公开(公告)号：US20150245467A1

公开(公告)日：2015-08-27

申请号：US14188998

申请日：2014-02-25

Applicant: MOTOROLA SOLUTIONS, INC

Inventor： KHAI LOKE LIM ,  KOW CHEE CHONG ,  MACWIEN KRISHNAMURTHI ,  SWEE THEAM THOR

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/42 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/0218 ,  H05K1/0366 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/0097 ,  H05K3/403 ,  H05K3/427 ,  H05K3/429 ,  H05K2201/0397 ,  H05K2201/09545 ,  H05K2201/1034 ,  H05K2203/063 ,  H05K2203/0703 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board includes at least one plated-through hole via drilled into at least one of a first layer on a first side of the printed circuit board and a second layer on a second side of the printed circuit board. The printed circuit board also includes a core section laminated between the first layer and the second layer, wherein a length of the core section is shorter than a length of the first layer and a length of the second layer. The printed circuit board further includes an open slot configured to house a connection tab of an electronic product connected to the printed circuit board, wherein the open slot is formed adjacent to the core section and between sections of the first layer and the second layer that are longer than the core section.

Abstract translation: 印刷电路板包括穿过印刷电路板的第一侧上的第一层和印刷电路板的第二面上的第二层中的至少一个的至少一个电镀通孔。 印刷电路板还包括层叠在第一层和第二层之间的芯部，其中芯部的长度短于第一层的长度和第二层的长度。 印刷电路板还包括开口槽，其构造成容纳连接到印刷电路板的电子产品的连接片，其中所述开口狭缝形成在所述芯部分附近以及在所述第一层和所述第二层的部分之间 比核心部分长。

公开(公告)号：US09078344B2

公开(公告)日：2015-07-07

申请号：US13484823

申请日：2012-05-31

Applicant: Kyung Don Mun ,  Kil Yong Yun

Inventor： Kyung Don Mun ,  Kil Yong Yun

IPC: H05K3/00 ,  H05K3/04 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K3/007 ,  H05K1/116 ,  H05K3/0097 ,  H05K3/045 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09545 ,  Y10T29/49126

Abstract: A printed circuit board includes: a first insulating layer; a second insulating layer of which one surface is formed to be in contact with the other surface of the first insulating layer; a first circuit pattern formed to be embedded in one surface of the first insulating layer; a second circuit pattern formed to be embedded between the first insulating layer and the second insulating layer; a third circuit pattern formed to be protruded from the other surface of the second insulating layer; and a landless fill-plating layer for filling a hole which penetrates the first insulating layer.

Abstract translation: 印刷电路板包括：第一绝缘层; 一个表面形成为与第一绝缘层的另一个表面接触的第二绝缘层; 形成为嵌入在所述第一绝缘层的一个表面中的第一电路图案; 形成为嵌入在所述第一绝缘层和所述第二绝缘层之间的第二电路图案; 形成为从所述第二绝缘层的另一个表面突出的第三电路图案; 以及用于填充贯穿第一绝缘层的孔的无地填充镀层。