公开(公告)号：WO2006069843A1

公开(公告)日：2006-07-06

申请号：PCT/EP2005/055725

申请日：2005-11-03

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  BUSCH, Georg

Inventor： BUSCH, Georg

IPC: H05K1/00 ,  H05K1/11

CPC classification number: H05K1/0287 ,  H05K1/0393 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09609

Abstract: Es wird ein Halbzeug (2) sowie eine damit gebildete Träger¬ komponente (1) für darauf platzierte elektrische Schaltungs¬ bilder vorgeschlagen, die kostengünstig und zeitsparend eine Prototypen- oder Kleinserien-Fertigung ermöglichen. Erreicht wird dies dadurch, dass das Halbzeug (2) ein flächig ausge¬ bildetes, zum Beispiel flexibles, Basisträgermaterial umfasst, über dessen gesamten Flächenbereich in einem gleichmä¬ ßigen konstanten Raster mit Nano-Vias gebildete Durchkontaktierungen (7) angeordnet sind. Eine solche Komponente ist mit einer einzigen Schablone für die Belichtung zur Bildung der Nano-Vias realisierbar. Mit einer solchen Komponente sind aber auch Schaltungsbilder beliebigen Aussehens auf deren Oberflächen herstellbar.

Abstract translation: 它是一种半成品（2），以及一个这样形成的Träger¬组分（1）为它，放置电Schaltungs¬图像，提出了使成本效益和原型或小批量生产节省时间的。 这是这样实现的半成品（2）包括一个平头ausge¬，灵活，例如，基底基板，在与纳米过孔的gleichmä¬拉尔恒定电网（7）被设置形成在整个表面面积的通孔。 这样的组件可以用单个掩模曝光，以形成纳米孔来实现。 有了这样一个分量，而且在其表面上的任何图像电路的外观可被制造。

公开(公告)号：WO2005081595A3

公开(公告)日：2005-12-15

申请号：PCT/US2005004468

申请日：2005-02-14

Applicant: MOLEX INC

Inventor： REGNIER KENT E ,  BRUNKER DAVID L ,  OGBUOKIRI MARTIN U

IPC: H01L23/64 ,  H01L23/66 ,  H01R12/16 ,  H01R13/658 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H01R24/00

CPC classification number: H05K1/0245 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board (200, 300, 400) design is disclosed that is useful in high speed differential signal applications uses either a via arrangement or a circuit trace exit structure. In the via arrangement, sets of differential signal pair vias (301, 303, 401, 402) and an associated ground (302) are arranged adjacent to each other in a repeating pattern. The differential signal vias (301, 303, 591) of each pair are spaced closer to their associated ground via (302a, 593a) than the spacing between the adjacent differential signal pair associated ground (302b, 593b) so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias. The circuit trace exit structure involves the exit portions of the circuit traces (420, 550) of the differential signal vias (401, 402, 591) to follow a path where the traces then meet with and join to the transmission line portions (552) of the conductive traces.

Abstract translation: 公开了一种在高速差分信号应用中使用通路布置或电路走线出口结构的电路板（200,300,400）设计。 在通孔布置中，差分信号对通孔（301,303,401,402）和相关联的接地（302）的组以重复图案彼此相邻布置。 每对的差分信号通孔（301,303,591）比相邻的差分信号对相关联的接地（302b，593b）之间的间隔更靠近其相关联的接地（302a，593a），使得差分信号通孔显示出 优选电耦合到其相关的接地通孔。 电路走线出口结构涉及差分信号通孔（401,402,591）的电路迹线（420,550）的出口部分，以跟随走线然后与路线相交并连接到传输线部分（552）的路径， 的导电迹线。

公开(公告)号：WO2005081595A2

公开(公告)日：2005-09-01

申请号：PCT/US2005/004468

申请日：2005-02-14

Applicant: MOLEX INCORPORATED

Inventor： REGNIER, Kent, E. ,  BRUNKER, David, L. ,  OGBUOKIRI, Martin, U.

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board design is disclosed that is useful in high speed differential signal applications uses either a via arrangement or a circuit trace exit structure. In the via arrangement, sets of differential signal pair vias and an associated ground are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair are spaced closer to their associated ground via than the spacing between the adjacent differential signal pair associated ground so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias. The circuit trace exit structure involves the exit portions of the circuit traces of the differential signal vias to follow a path where the traces then meet with and join to the transmission line portions of the conductive traces.

Abstract translation: 公开了一种在高速差分信号应用中使用电路布置或电路走线出口结构的电路板设计。 在通孔布置中，差分信号对通孔和相关接地的组以重复图案彼此相邻布置。 每对的差分信号通孔比相邻的差分信号对相关联的接地之间的间隔更靠近其相关联的接地间隔，使得差分信号通孔表现出对它们相关的接地通孔的电耦合的偏好。 电路走线出口结构涉及差分信号通孔的电路迹线的出口部分，以跟随路径，其中迹线然后与导电迹线的传输线部分相接合并连接到导体迹线的传输线部分。

公开(公告)号：WO2004098256A1

公开(公告)日：2004-11-11

申请号：PCT/SE2004/000606

申请日：2004-04-21

Applicant: SENSEAIR AB ,  MARTIN, Hans Göran Evald ,  HJORT, Klas Anders ,  LINDBERG, Mikael Peter Erik

Inventor： MARTIN, Hans Göran Evald ,  HJORT, Klas Anders ,  LINDBERG, Mikael Peter Erik

IPC: H05K3/18

CPC classification number: H05K3/0041 ,  G01K2211/00 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/002 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2203/092 ,  H01L2924/00

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10-V60) are chosen having mutually different thermoelectric properties. A material surface-applied to the thin film substrate, coated on both sides (10a, 10b) of the thin film substrate (10), is distributed and/or adapted in order to allow the electrical interconnection of first vias, allocated the first material (M1), with second vias, allocated the second material (M2), and that a first via (V10) included in a series connection and a last via (V60) included in the series connection are serially co-ordinated in order to form an electric thermocouple (100) or other circuit arrangement.

Abstract translation: 本发明包括一种处理过的薄膜基片（10）及一种方法，为了制造柔性印刷电路卡，具有多个微孔穿过或穿过薄膜基片并沿着相对表面电连接， 以形成电路。 第一数量的真实纳米轨迹填充有具有良好电性能的第一材料（M1），用于形成第一数量的这里计数的第一通孔（V10，V30，V50），第二数量 的真实纳米轨迹填充有具有良好电性能的第二材料（M2），用于形成第二数量的这里计数的第二通孔（V20，V40，V60）。 选择所述第一和第二通孔（V10-V60）的第一材料（M1）和第二材料（M2）具有彼此不同的热电性质。 在薄膜基板（10）的两侧（10a，10b）上涂覆表面施加到薄膜基板的材料被分布和/或适配，以便允许分配第一材料的第一通孔的电互连 （M1），具有第二通孔，分配第二材料（M2），并且串联连接中包括的第一通孔（V10）和串联连接中包括的最后通路（V60）被串联以形成 电热电偶（100）或其他电路装置。

公开(公告)号：WO2004045262A1

公开(公告)日：2004-05-27

申请号：PCT/US2003/035501

申请日：2003-11-07

Applicant: PPG INDUSTRIES OHIO, INC.

Inventor： OLSON, Kevin, C. ,  WANG, Alan, E.

IPC: H05K3/44

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract translation: 提供了用于制造多层电路组件的工艺和通过这些工艺制造的多层电路组件。 该方法包括（a）提供基底，其至少一个区域包括多个通孔，这些区域的通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; 和（c）在基片的所有表面上施加一层金属。 可以包括诸如电路化的附加处理步骤。

公开(公告)号：WO1993026143A1

公开(公告)日：1993-12-23

申请号：PCT/CH1993000145

申请日：1993-06-09

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K03/00

CPC classification number: H05K3/4655 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/4084 ,  H05K3/42 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4635 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09572 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917

Abstract: The initial intention in the semi-finished product of the invention is to provide a functional separation between the requirement for mechanical strength and the previously concomitant requirement, for completing a circuit, in order to bring the pure circuit connection, especially for signals, "closer" to the electrical and technical properties of chips. To do this, the layout miniaturisation is optimised without regard for the mechanical strength of the substrate. Instead of a printed circuit board (MCM), a semi-finished product which can be developed into a printed circuit board is made. The semi-finished product of the invention consists of an extremely thin film (8) with a plurality of extremely small holes (14) made simultaneously by an etching process. The hole diameters can be reduced by almost an order of magnitude (down to 20 mu m), facilitating, for instance, definite sub-100 mu m technology. Such a semi-finished product (19) does not act as a mechanical support but is designed only for signal conduction. The semi-finished product (19) which carries the densely packed wiring pattern, is bonded to a not densely packed power supply plane (22) acting as the service plane and the printed circuit board thus made is finally secured to a mechanical support (20).

公开(公告)号：JPWO2017068917A1

公开(公告)日：2018-06-28

申请号：JP2016078377

申请日：2016-09-27

Applicant: シャープ株式会社

Inventor： 中西 宏之 ,  佐藤 知稔

IPC: H01L23/15 ,  H01L23/12 ,  H01L25/07 ,  H01L25/18 ,  H01L23/36 ,  H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0271 ,  H01L23/12 ,  H01L23/15 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/19105 ,  H05K1/02 ,  H05K1/0201 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/142 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10522 ,  H01L2924/00014

Abstract: ガラスからなる支持基板(11)と、支持基板(11)の第1面(11a)に配置されている第1回路部(20)と、支持基板(11)の第2面(11b)に配置されている第2回路部(30)とを備え、第2回路部(30)には複数のスリット(32)からなる抜きパターン(31、33〜35)が形成されているガラス配線基板。

公开(公告)号：JP6013960B2

公开(公告)日：2016-10-25

申请号：JP2013068185

申请日：2013-03-28

Applicant: 京セラ株式会社

Inventor： 福島 啓之 ,  雲川 文夫

IPC: H01L23/12 ,  H05K3/46

CPC classification number: H05K3/4602 ,  H01L24/81 ,  H05K1/0271 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K3/3436 ,  H05K3/4644

公开(公告)号：JP2015041630A

公开(公告)日：2015-03-02

申请号：JP2013170366

申请日：2013-08-20

Applicant: 新光電気工業株式会社 ,  Shinko Electric Ind Co Ltd

Inventor： KUNIMOTO YUJI ,  SHIMIZU NORIYOSHI

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4602 ,  H05K2201/09518 ,  H05K2201/09609

Abstract: 【課題】配線層の微細化に容易に対応することができる配線基板を提供する。【解決手段】配線基板10は、配線層72を被覆する絶縁層82と、絶縁層82の上面82Aに開口し、配線層72の表面を露出する貫通孔VH9と、貫通孔VH9を充填するビアV9と、ビアV9と接続されるとともに、絶縁層82上に積層されたプレーン層74と、を有する。また、配線基板10は、プレーン層74の上面に開口し、絶縁層82の上面82Aを露出する貫通孔74Xと、貫通孔74Xを充填するとともに、プレーン層74を被覆する絶縁層83と、絶縁層83上に積層された信号配線76と、を有する。そして、貫通孔VH9は、信号配線76と平面視で重なる位置に形成され、貫通孔74Xは、信号配線76と平面視で重ならない位置に形成されている。【選択図】図1

Abstract translation: 要解决的问题：提供一种可以容易地处理布线层的小型化的布线板。解决方案：布线板10包括：覆盖布线层72的绝缘层82; 在绝缘层82的上表面82A上开口的通孔VH9，并露出布线层72的表面; 填充通孔VH9的通孔V9; 以及与通孔V9连接并叠层在绝缘层82上的平面层74.另外，布线板10具有：在平面层74的上表面上开口的通孔74X，露出上述表面82A， 绝缘层82; 填充通孔74X并涂覆平面层74的绝缘层83; 和层叠在绝缘层83上的信号布线76.通孔VH9形成在与信号布线76重叠的位置，平面图中，并且通孔74X形成在与信号布线76不重叠的位置 在平面图中。

公开(公告)号：JP2014192432A

公开(公告)日：2014-10-06

申请号：JP2013068185

申请日：2013-03-28

Applicant: Kyocer Slc Technologies Corp ,  京セラSlcテクノロジー株式会社

Inventor： FUKUSHIMA NORIYUKI ,  KUMOKAWA FUMIO

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H05K3/4602 ,  H01L24/81 ,  H05K1/0271 ,  H05K3/3436 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09781

Abstract: PROBLEM TO BE SOLVED: To provide a wiring board which eliminates an electrical short circuit between solder bumps caused by warpage and which can cause a mounting semiconductor element to normally operate.SOLUTION: A wiring board comprises: a core substrate 1 having a number of through holes 5; build-up insulation layers 2 and build-up wiring layers 3 which are alternately laminated one on top of the other on each of the top face and an undersurface of the core substrate 1; semiconductor element connection pad formation regions on a top face central part, in which a number of semiconductor element connection pads 7 are arranged in a reticular pattern; first through holes arranged in a first region X in the core substrate 1 opposite to the semiconductor element connection pad formation region A with a first arrangement density; second through holes arranged in each second region Y on an outer periphery of the core substrate 1 and at a distance from the first region X with a second arrangement density lower than the first arrangement density; and third through holes arranged in each third region Z between the first region X and the second region Y with a third arrangement density higher than the second arrangement density.

Abstract translation: 要解决的问题：提供一种消除由翘曲引起的焊料凸块之间的电短路并能够使半导体元件正常工作的布线板。解决方案：布线板包括：芯基板1，其具有多个通孔 孔5; 在芯基板1的上表面和下表面之间交替层叠一层叠层的积层绝缘层2和堆积布线层3; 半导体元件连接焊盘形成区域在顶面中心部分，其中多个半导体元件连接焊盘7以网状图案布置; 第一通孔，以第一配置密度布置在芯基板1中的与半导体元件连接焊盘形成区域A相对的第一区域X中; 第二通孔布置在芯基板1的外周上的每个第二区域Y中，并且距第一区域X一定距离，第二布置密度低于第一布置密度; 以及第三通孔，其布置在第一区域X和第二区域Y之间的每个第三区域Z中，第三布置密度高于第二布置密度。