公开(公告)号：EP3174825B1

公开(公告)日：2018-06-06

申请号：EP15739302.6

申请日：2015-07-24

Applicant: ams International AG

Inventor： BESLING, Willem Frederik Adrianus ,  PIJNENBURG, Remco Henricus Wilhelmus ,  VAN DER AVOORT, Casper ,  OLDSEN, Marten ,  GOOSSENS, Martijn

IPC: B81C1/00 ,  G01L9/00

CPC classification number: B81C1/00158 ,  B81C1/00246 ,  B81C2201/014 ,  G01L9/0042 ,  G01L9/0072 ,  G01L9/0073 ,  G01L9/12 ,  H01L29/84

Abstract: Embodiments of a method for forming a suspended membrane include depositing a first electrically conductive material above a sacrificial layer and within a boundary trench. The first electrically conductive material forms a corner transition portion above the boundary trench. The method further includes removing a portion of the first electrically conductive material that removes at least a portion of uneven topography of the first electrically conductive material. The method further includes depositing a second electrically conductive material. The second electrically conductive material extends beyond the boundary trench. The method further includes removing the sacrificial layer through etch openings and forming a cavity below the second electrically conductive material. The first electrically conductive material defines a portion of a sidewall boundary of the cavity.

公开(公告)号：EP3321655A1

公开(公告)日：2018-05-16

申请号：EP17201370.8

申请日：2017-11-13

Applicant: Rosemount Aerospace Inc.

Inventor： POTASEK, David P. ,  HOULIHAN, Sean

IPC: G01L9/00

CPC classification number: B81B3/0086 ,  B81B3/0081 ,  B81B2201/0264 ,  B81B2207/07 ,  B81C1/00269 ,  B81C2201/013 ,  B81C2201/014 ,  G01L9/0047 ,  G01L9/0073

Abstract: A configuration for a capacitive pressure sensor uses a silicon on insulator wafer to create an electrically isolated sensing node across a gap from a pressure sensing wafer. The electrical isolation, small area of the gap, and silicon material throughout the capacitive pressure sensor allow for minimal parasitic capacitance and avoid problems associated with thermal mismatch.

Abstract translation: 用于电容式压力传感器的配置使用绝缘体上硅晶片来跨压力感测晶片的间隙形成电隔离感测节点。 整个电容式压力传感器的电气隔离，间隙的小面积和硅材料允许最小的寄生电容并避免与热失配相关的问题。

公开(公告)号：EP3290389A1

公开(公告)日：2018-03-07

申请号：EP17186434.1

申请日：2017-08-16

Applicant: Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

Inventor： WANG, Xianchao

IPC: B81C1/00

CPC classification number: H01L21/76804 ,  B81B2201/0257 ,  B81C1/00587 ,  B81C2201/014 ,  H01L21/02326 ,  H01L21/02505 ,  H01L21/3205 ,  H01L21/56 ,  H01L23/5329 ,  H01L29/4232 ,  H01L2924/0002

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a capping layer having a plurality of steps on the protective layer covering the semiconductor substrate; and removing at least one layer of the multilayer film to form a cavity that is defined by the capping layer and a remaining multilayer film that has the at least one layer removed. The thus formed semiconductor device does not have cracks in the steps of the capping layer when performing an etch process, thereby improving the performance of the semiconductor device.

Abstract translation: 一种用于制造半导体器件的方法包括：提供半导体衬底，该半导体衬底包括衬底和在衬底上具有阶梯形部分的多层膜; 形成覆盖多层膜的台阶状部分的保护层; 在覆盖半导体衬底的保护层上形成具有多个台阶的覆盖层; 以及去除多层膜的至少一个层以形成由封盖层和具有去除的至少一个层的剩余多层膜限定的空腔。 由此形成的半导体器件在执行刻蚀工艺时在封盖层的步骤中不具有裂缝，从而改善了半导体器件的性能。

公开(公告)号：EP3109200A1

公开(公告)日：2016-12-28

申请号：EP16170650.2

申请日：2016-05-20

Applicant: Nivarox-FAR S.A.

Inventor： Gandelhman, Alex ,  Pin, André

IPC: B81C99/00 ,  B81C1/00

CPC classification number: B81C1/00619 ,  B81B2201/035 ,  B81B2203/0384 ,  B81C1/00103 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0138 ,  B81C2201/014 ,  B81C2201/0188 ,  B81C2201/0198 ,  G04B13/02 ,  G04B13/026 ,  G04B13/027 ,  G04D99/00

Abstract: L'invention se rapporte à une pièce à base de silicium avec au moins une surface de contact diminuée qui, formée à partir d'un procédé combinant au moins une étape de gravage de flancs obliques avec un gravage du type « Bosch » de flancs verticaux, permet notamment l'amélioration tribologique de pièces formées par micro-usinage d'une plaquette à base de silicium.

Abstract translation: 本发明涉及一种具有至少一个还原接触表面的硅基组分，其通过将至少一个斜侧壁蚀刻步骤与垂直侧壁的“博世”蚀刻相结合的方法形成，特别是改进了摩擦学 通过微加工硅基晶片形成的部件。

公开(公告)号：EP2973665A4

公开(公告)日：2016-11-16

申请号：EP14770043

申请日：2014-03-08

Applicant: BOSCH GMBH ROBERT

Inventor： GRAHAM ANDREW ,  YAMA GARY ,  O'BRIEN GARY

IPC: H01L21/28

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  B81B2203/04 ,  B81B2203/053 ,  B81C1/00095 ,  B81C1/00166 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0177 ,  B81C2203/0136

Abstract: In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop.

Abstract translation: 在一个实施例中，形成平面外电极的方法包括在器件层的上表面上形成氧化物层，蚀刻限定延伸穿过氧化物层的沟槽的蚀刻停止周界，在第一帽层部分上形成 氧化层的上表面和蚀刻停止周界界定沟槽内，蚀刻延伸穿过第一覆盖层部分并停止在氧化物层处的第一电极周界，限定沟槽，在第一电极周界界定槽内沉积第一材料部分，沉积 在沉积的第一材料部分上方的第二盖层部分，以及用蚀刻停止部分提供横向蚀刻停止的部分氧化物层的蒸气。

公开(公告)号：EP1657553B1

公开(公告)日：2016-08-31

申请号：EP06001027.9

申请日：2000-04-14

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Oguchi, Takahiro, (A170) Intell., Prop., Dept.

IPC: G01P15/08

CPC classification number: G01C19/5719 ,  B81B2201/025 ,  B81C1/00579 ,  B81C1/00587 ,  B81C2201/0132 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S148/159

公开(公告)号：EP2969911A1

公开(公告)日：2016-01-20

申请号：EP14775941.9

申请日：2014-03-12

Applicant: Robert Bosch GmbH

Inventor： FEYH, Ando ,  GRAHAM, Andrew

IPC: B81B3/00 ,  B81B7/00 ,  H04R19/00

CPC classification number: H04R19/04 ,  B81B7/02 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/0714 ,  H04R19/005 ,  H04R31/00

Abstract: A microelectromechanical system (MEMS) microphone has a substrate including a backside trench, and a flexible membrane deposited on the substrate extending over the backside trench. The flexible membrane includes a first electrode. A silicon spacer layer is deposited on a perimeter portion of the flexible membrane. The spacer layer defines an acoustic chamber above the membrane and the backside trench. A silicon rich silicon nitride (SiN) backplate layer is deposited on top of the silicon spacer layer extending over the acoustic chamber. The backplate defines a plurality of opening into the acoustic chamber and includes a metallization that serves as a second electrode.

公开(公告)号：EP2803635A2

公开(公告)日：2014-11-19

申请号：EP14168566.9

申请日：2014-05-16

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Gu-Stoppel, Shanshan ,  Quenzer, Hans Joachim ,  Hofmann, Ulrich

IPC: B81C1/00

CPC classification number: B81B3/0027 ,  B81B3/0029 ,  B81B2201/042 ,  B81B2203/0109 ,  B81B2203/0163 ,  B81C1/00357 ,  B81C1/00626 ,  B81C2201/014 ,  H01L29/84

Abstract: Die Erfindung bezieht sich auf eine MEMS-Struktur mit einem Stapel aus unterschiedlichen Schichten und einem in der Dicke variierenden Feder-Masse-System, welches aus dem Stapel gebildet wird und bei dem von einer Rückseite des Stapels und des Substrats aus an lateral unterschiedlichen Stellen das Substrat unter Verbleib der ersten Halbleiter-schicht respektive das Substrat, die erste Ätzstoppschicht und die erste Halbleiterschicht entfernt sind, sowie ein Verfahren zum Herstellen einer solchen Struktur.

Abstract translation: 本发明涉及一种在MEMS结构具有由不同层的叠层和一个弹簧 - 质量系统在其厚度变化的所有其上形成有堆叠的，并worin，从堆栈和所述基板的背面侧开始，在晚的反弹 不同的位置，同时使所述第一半导体层，或基底，所述第一蚀刻停止层和所述第一半导体层的衬底被除去，以及一种用于制造结构的搜索的方法。

公开(公告)号：EP1425241B1

公开(公告)日：2013-11-27

申请号：EP02754965.8

申请日：2002-07-31

Applicant: Infineon Technologies AG

Inventor： AIGNER, Robert ,  PLÖTZ, Florian

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00158 ,  B81C2201/014 ,  H01L21/764 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2399863A1

公开(公告)日：2011-12-28

申请号：EP10166782.2

申请日：2010-06-22

Applicant: VALTION TEKNILLINEN TUTKIMUSKESKUS

Inventor： Puurunen, Riikka ,  Henttinen, Kimmo ,  Kattelus, Hannu ,  Suni, Tommi

IPC: B81C1/00

CPC classification number: H01L21/0228 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2201/0167 ,  B81C2201/053 ,  B81C2203/0118 ,  H01L29/02

Abstract: A method for manufacturing a multi-layer substrate structure comprising obtaining a first and second wafer, such as two silicon wafers, wherein at least one of the wafers may be optionally provided with a material layer such as an oxide layer (302, 404), forming a cavity on the bond side of the first wafer (306, 406), depositing, preferably by ALD (Atomic Layer Deposition), a material layer, such as alumina layer, on either wafer arranged so as to at least in places face the other wafer and cover at least portion of the cavity of the first wafer, such as bottom, wall and/or edge thereof, and enable stopping etching, such as plasma etching, into the underlying material (308, 408), and bonding the wafers provided with at least the aforesaid ALD layer as an intermediate layer together to form the multi-layer semiconductor substrate structure (310, 312). A related multi-layer substrate structure is presented.

Abstract translation: 一种用于制造多层衬底结构的方法，包括获得第一和第二晶片，例如两个硅晶片，其中至少一个晶片可以可选地设置有诸如氧化物层（302,404）的材料层， 在第一晶片（306,406）的接合侧上形成空腔，优选地通过ALD（原子层沉积）沉积材料层，例如氧化铝层，在任一晶片上布置，至少在面向 其他晶片并且覆盖第一晶片的空腔的至少部分，例如其底部，壁和/或边缘，并且使得能够停止诸如等离子体蚀刻的蚀刻到下面的材料（308,408）中，并且将晶片 至少设置上述ALD层作为中间层，以形成多层半导体衬底结构（310,312）。 提出了相关的多层基板结构。