公开(公告)号：US3753816A

公开(公告)日：1973-08-21

申请号：US3753816D

申请日：1971-11-18

Applicant: RCA CORP

Inventor： FELDSTEIN N ,  LAW H

IPC: C23C18/18 ,  G03F1/72 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/22 ,  C23F1/02 ,  C23F17/00

CPC classification number: G03F1/72 ,  C23C18/1605 ,  H05K1/0306 ,  H05K3/062 ,  H05K3/108 ,  H05K3/181 ,  H05K3/225 ,  H05K2201/0344 ,  H05K2203/0542 ,  H05K2203/072 ,  Y10T29/49156 ,  Y10T29/49746

Abstract: The method comprises depositing a thin layer of a first metal having a relatively high degree of solubility in a particular etchant over both plated areas (if a previously deposited pattern is being repaired) and unplated areas on a substrate, this first metal being catalytic to electroless deposition of a second metal to be subsequently deposited, electrolessly depositing on the first metal either an overall pattern of areas of a second metal which has a relatively low degree of solubility in the etchant or a pattern limited to parts of a previously deposited pattern that were missing or incompletely formed, and then treating the plated areas with the etchant, where desired, so that the first metal is removed where it is not covered by the second metal but the second metal is substantially unaffected.

Abstract translation: 该方法包括在两个镀覆区域（如果先前沉积的图案被修复）和在基底上未镀覆的区域上沉积具有相对较高溶解度的第一金属薄层，该第一金属在特定的蚀刻剂上催化以无电化 沉积待随后沉积的第二金属，在第一金属上无电沉积第二金属的整体图案，其在蚀刻剂中具有相对较低溶解度的第二金属的区域或限于先前沉积图案的部分的图案， 丢失或不完全形成，然后在需要时用蚀刻剂处理镀覆区域，使得第一金属在不被第二金属覆盖但第二金属基本上不受影响的情况下被去除。

公开(公告)号：US3377259A

公开(公告)日：1968-04-09

申请号：US43966965

申请日：1965-03-15

Applicant: GEN DYNAMICS CORP

Inventor： EUGENE PHILLIPS

IPC: C25D5/56 ,  H01B1/00 ,  H01P11/00 ,  H05K1/03 ,  H05K3/18 ,  H05K3/38

CPC classification number: H05K3/384 ,  C25D5/56 ,  H01B1/00 ,  H01P11/00 ,  H05K1/032 ,  H05K3/181 ,  H05K2201/0158 ,  H05K2201/0344 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10S205/927 ,  Y10S428/934 ,  Y10S428/935 ,  Y10S428/936 ,  Y10S428/941 ,  Y10T428/12486 ,  Y10T428/12556 ,  Y10T428/12569 ,  Y10T428/12778 ,  Y10T428/12896 ,  Y10T428/12903 ,  Y10T428/12986 ,  Y10T428/31692

公开(公告)号：US2699425A

公开(公告)日：1955-01-11

申请号：US29728552

申请日：1952-07-05

Applicant: MOTOROLA INC

Inventor： TEMPLE NIETER

IPC: H05K3/10 ,  H05K3/18 ,  H05K3/28 ,  H05K3/34 ,  H05K3/42

CPC classification number: H05K3/3489 ,  H05K3/108 ,  H05K3/181 ,  H05K3/282 ,  H05K3/426 ,  H05K2201/0344 ,  H05K2203/075 ,  Y10T29/49155

公开(公告)号：US2699424A

公开(公告)日：1955-01-11

申请号：US12016549

申请日：1949-10-07

Applicant: MOTOROLA INC

Inventor： TEMPLE NIETER

IPC: H05K3/10 ,  H05K3/18 ,  H05K3/42

CPC classification number: H05K3/108 ,  H05K3/188 ,  H05K3/426 ,  H05K2201/0344 ,  H05K2203/0315 ,  H05K2203/1142

公开(公告)号：US20240206062A1

公开(公告)日：2024-06-20

申请号：US18565613

申请日：2022-06-27

Applicant: Lotte Energy Materials Corporation

Inventor： Chang Yol YANG ,  Won Jin BEOM ,  Hyung Cheol KIM ,  Kideok SONG

IPC: H05K1/09 ,  H05K3/06

CPC classification number: H05K1/09 ,  H05K3/062 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/0355 ,  H05K2203/0323 ,  H05K2203/0353 ,  H05K2203/0384

Abstract: Disclosed are an ultra-thin copper foil with a carrier foil and a method for manufacturing an embedded substrate by using the same, the ultra-thin copper foil with a carrier foil including: a carrier foil; a non-etching release layer on the carrier foil; a first ultra-thin copper foil layer on the non-etching release layer; an etch stop layer on the first ultra-thin copper foil layer; and a second ultra-thin copper foil layer on the etch stop layer.

公开(公告)号：US20240114630A1

公开(公告)日：2024-04-04

申请号：US18479767

申请日：2023-10-02

Applicant: Meta Platforms Technologies, LLC

Inventor： Cameron Elliot Glasscock ,  Zhenzhen Shen ,  Felippe Jose Pavinatto ,  Omar Awartani ,  Allison Tuuri ,  Lichuan Chen ,  Aleksey Reiderman ,  Marcos Antonio Santana Andrade, JR.

IPC: H05K3/32 ,  H05K1/02 ,  H05K3/18

CPC classification number: H05K3/326 ,  H05K1/0272 ,  H05K1/028 ,  H05K1/0289 ,  H05K3/181 ,  H05K2201/0344

Abstract: The present disclosure provides systems, methods, and devices for producing an interconnect. An electronic device of the present disclosure includes a deformable substrate including a circuit. The circuit includes a channel extending from a first portion of the deformable substrate to a second portion of the deformable substrate. A first circuit component is adjacent to the first portion of the deformable substrate. A second circuit component is adjacent to the second portion of the deformable substrate. A first metal material is formed overlaying a first portion of the deformable substrate including a first portion of the channel. A second metal material interfaces with the first metal material, thereby substantially occupying an interior volume of the channel.

公开(公告)号：US20170303401A1

公开(公告)日：2017-10-19

申请号：US15609047

申请日：2017-05-31

Applicant: HSIO Technologies, LLC

Inventor： James J. Rathburn

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H05K3/10 ,  H05K1/16

CPC classification number: H05K1/181 ,  B33Y80/00 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0221 ,  H05K1/0256 ,  H05K1/0274 ,  H05K1/0284 ,  H05K1/118 ,  H05K1/16 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/246 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2201/0344 ,  H05K2201/0367 ,  H05K2201/09109 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

公开(公告)号：US09609751B2

公开(公告)日：2017-03-28

申请号：US14251486

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H01L23/498

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

公开(公告)号：US09288901B2

公开(公告)日：2016-03-15

申请号：US14264499

申请日：2014-04-29

Applicant: Roger G. Markham ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

Inventor： Roger G. Markham ,  Ronald Steven Cok ,  Yongcai Wang ,  Mitchell Lawrence Wright

IPC: H01L33/42 ,  H05K1/02 ,  H01B1/02 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K1/0298 ,  H01B1/02 ,  H05K1/0293 ,  H05K1/097 ,  H05K1/165 ,  H05K3/103 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/181 ,  H05K3/246 ,  H05K3/247 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/10098 ,  H05K2203/1476 ,  H05K2203/173

Abstract: A thin-film multi-layer micro-wire structure includes a substrate and a layer located on the substrate or forming a part of the substrate. One or more micro-channels are located in the layer. Each micro-channel has a width less than or equal to 20 microns. A cured electrically conductive micro-wire is located only within each micro-channel. The micro-wire has a thickness less than or equal to 20 microns, including silver nano-particles, and having a percent ratio of silver that is greater than or equal to 40% by weight. An electrolessly plated layer is located at least partially within each micro-channel between the micro-wire and the layer surface and in electrical contact with the micro-wire. The plated layer has a thickness less than a thickness of the micro-wire so that the micro-wire and plated layer form the thin-film multi-layer micro-wire.

Abstract translation: 薄膜多层微线结构包括衬底和位于衬底上或形成衬底的一部分的层。 一个或多个微通道位于该层中。 每个微通道具有小于或等于20微米的宽度。 固化的导电微线仅位于每个微通道内。 微线具有小于或等于20微米的厚度，包括银纳米颗粒，并且银的百分比大于或等于40重量％。 无电镀层至少部分地位于微线和层表面之间的每个微通道内并与微线电接触。 电镀层的厚度小于微线的厚度，使得微线和镀层形成薄膜多层微线。

公开(公告)号：US09184135B1

公开(公告)日：2015-11-10

申请号：US14569010

申请日：2014-12-12

Applicant: Triton Microtechnologies

Inventor： Tim Mobley ,  Roupen Leon Keusseyan ,  Charles Tucker

IPC: H01L23/538 ,  H05K3/00 ,  H05K1/03 ,  H05K1/09 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13138 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/007 ,  H05K2201/0344 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/11009 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2224/45099

Abstract: A system for backside metallization and reinforcement of glass substrates to provide support and protection during handling and processing of the glass substrates. A sacrificial substrate is removeably attached to a glass substrate comprising through-holes, backside metallized pads, and under-bump metallization (UBM) pads enclosing the backside metallized pads. The sacrificial substrate comprises a sacrificial layer, an opaque film, and an adhesive. The sacrificial substrate protects the backside metallized pads and UBM pads, and reinforces the glass substrate.

Abstract translation: 用于玻璃基板的背面金属化和增强的系统，以在玻璃基板的处理和加工期间提供支撑和保护。 牺牲衬底可移除地附接到包括通孔，背面金属化焊盘和包围背面金属化焊盘的凸起下金属化（UBM）焊盘的玻璃衬底。 牺牲衬底包括牺牲层，不透明膜和粘合剂。 牺牲基板保护背面金属化焊盘和UBM焊盘，并加强玻璃基板。