公开(公告)号：US20150075843A1

公开(公告)日：2015-03-19

申请号：US14389387

申请日：2013-03-27

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Hiroyuki Yamaguchi ,  Seiichi Kurihara ,  Hiroshi Sakurai ,  Shunsuke Nukina

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0154 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2201/10287 ,  H05K2203/061 ,  H05K2203/1572

Abstract: A multilayer wiring board includes a first metal foil wiring layer that has at least two or more layers of metal foil wiring lines and is arranged on a mounting surface side for mounting a surface mount type component, a wire wiring layer that is arranged on an opposite side of the mounting surface, and in which an insulation coating wire is wired, and a first interlayer conduction hole that has a conduction part which electrically connects the metal foil wiring line positioned on a surface of the first metal foil wiring layer to at least one of the metal foil wiring line in an inner layer of the first metal foil wiring layer and the insulation coating wire of the wire wiring layer. A hole diameter of the first interlayer conduction hole varies in a board thickness direction of the multilayer wiring board.

Abstract translation: 多层布线基板包括：第一金属箔布线层，其具有至少两层以上的金属箔布线，并且布置在用于安装表面安装型部件的安装表面侧上，布线层布置在相对的布线层上 并且其中布置有绝缘涂层线的第一层导电孔和具有将位于第一金属箔布线层的表面上的金属箔布线与第一金属箔布线层的至少一个电连接的导电部的第一层间导电孔 的第一金属箔布线层的内层中的金属箔布线和布线层的绝缘涂层线。 第一层间导电孔的孔径在多层布线基板的板厚方向上变化。

公开(公告)号：US20150047892A1

公开(公告)日：2015-02-19

申请号：US14519677

申请日：2014-10-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongxing Yang ,  Feng Gao ,  Mingli Huang

IPC: H05K3/00 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K3/0047 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2203/0207 ,  Y10T29/49156

Abstract: A printed circuit board (PCB) backdrilling method is disclosed, where a conductive layer is disposed between a surface of a PCB on an intended-for-backdrilling side of a plated through hole (PTH) and a target signal layer of the PCB, and the method includes: performing a first backdrilling on the PTH with a first preset depth starting from the surface of the PCB; controlling the backdrill bit to move along the drill hole formed in the first backdrilling toward the target signal layer; and when the backdrill bit is in contact with the conductive layer, completing a second backdrilling with a second preset depth starting from the conductive layer.

Abstract translation: 公开了一种印刷电路板（PCB）回钻方法，其中将导电层设置在电镀通孔（PTH）的预期的后向钻孔侧的PCB的表面与PCB的目标信号层之间，以及 该方法包括：以从PCB的表面开始的第一预设深度在PTH上执行第一次回钻; 控制回钻头沿着形成在第一反向钻削中的钻孔朝向目标信号层移动; 并且当所述反钻头与所述导电层接触时，从所述导电层开始以第二预设深度完成第二次回钻。

公开(公告)号：US20150014044A1

公开(公告)日：2015-01-15

申请号：US13941644

申请日：2013-07-15

Applicant: International Business Machines Corporation

Inventor： Eric R. Ao ,  Donald R. Dignam ,  Stephen J. Flint

IPC: H05K3/00 ,  H05K1/11

CPC classification number: H05K3/0005 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09545

Abstract: A method is used for designing a multilayered circuit substrate that generates a physical design layout. The physical design layout represents of at least one electrical circuit passing through a plurality of layers. Based on performance requirements of the electrical circuit, a maximum allowable stub length of a via in the electrical circuit is computed. The computer processor determines if a stub length of an existing via in the physical design layout of the electrical circuit is less than the maximum allowable stub length. If the computer determines that the stub length of the existing via is less than the maximum allowable stub length, the computer removes an external non-functional pad of the existing via from the physical design layout.

Abstract translation: 一种方法用于设计生成物理设计布局的多层电路基板。 物理设计布局表示通过多个层的至少一个电路。 根据电路的性能要求，计算电路中通孔的最大容许短截线长度。 计算机处理器确定电路的物理设计布局中现有通孔的短截线长度是否小于最大允许短截线长度。 如果计算机确定现有通孔的短线长度小于最大允许短截线长度，则计算机将从物理设计布局中删除现有通孔的外部非功能焊盘。

公开(公告)号：US08933556B2

公开(公告)日：2015-01-13

申请号：US12895126

申请日：2010-09-30

Applicant: Nobuyuki Naganuma ,  Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Nobuyuki Naganuma ,  Michimasa Takahashi ,  Masakazu Aoyama

IPC: H01L23/053 ,  H01L23/12 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/116 ,  H05K1/18 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/4069 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09854 ,  Y10T156/1056

Abstract: A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from the first surface toward the second surface. The first insulation layer has a first hole which penetrates through the first insulation layer and includes a first conductor made of a plating in the first hole. The second insulation layer has a second hole which penetrates through the second insulation layer and includes a second conductor made of a conductive paste in the second hole. The third insulation layer has a third hole which penetrates through the third insulation layer and includes a third conductor made of a plating in the third hole. The first, second and third conductors are positioned along the same axis and are electrically continuous with each other.

Abstract translation: 布线板包括具有第一表面和第二表面并且包括第一，第二和第三绝缘层从第一表面朝向第二表面的顺序的层叠体。 第一绝缘层具有穿过第一绝缘层的第一孔，并且包括在第一孔中由电镀制成的第一导体。 第二绝缘层具有穿过第二绝缘层的第二孔，并且包括在第二孔中由导电膏制成的第二导体。 第三绝缘层具有穿过第三绝缘层的第三孔，并且包括在第三孔中由电镀制成的第三导体。 第一，第二和第三导体沿着相同的轴定位并且彼此电连续。

公开(公告)号：US20140247572A1

公开(公告)日：2014-09-04

申请号：US14279465

申请日：2014-05-16

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Motoo ASAI ,  Dongdong WANG ,  Hideo YABASHI ,  Seiji SHIRAI

IPC: H05K1/18

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract translation: 印刷电路板包括容纳层，容纳层中容纳的片状电容器器件，以及形成在容纳层上的堆积结构，使得堆积结构覆盖容纳层中的片状电容器器件。 积层结构具有安装导体结构，其被定位成将IC芯片装置安装在积层结构的表面上，使得IC芯片装置直接安装在芯片电容器装置上，每个芯片电容器装置具有电介质体， 所述积聚结构，形成在所述电介质体上且在所述电介质体的表面上延伸的第一电极，以及形成在所述电介质体上并在所述电介质体的表面上延伸的第二电极，并且所述电介质体介于所述第一电极 电极和第二电极。

公开(公告)号：US20130128472A1

公开(公告)日：2013-05-23

申请号：US13484823

申请日：2012-05-31

Applicant: Kyung Don MUN ,  Kil Yong Yun

Inventor： Kyung Don MUN ,  Kil Yong Yun

IPC: H05K7/06 ,  H05K3/36

CPC classification number: H05K3/007 ,  H05K1/116 ,  H05K3/0097 ,  H05K3/045 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09545 ,  Y10T29/49126

Abstract: The present invention discloses a printed circuit board and a manufacturing method thereof. The manufacturing method of the printed circuit board includes: forming a first circuit pattern on a metal layer formed on one surface of a base substrate; forming a second circuit pattern after laminating a first insulating layer in which the first circuit pattern is embedded; sequentially laminating a second insulating layer and a preliminary third circuit pattern on the second circuit pattern; separating the base substrate and forming a hole in the separated substrate; and forming a third circuit pattern, a landless first fill-plating layer, and a second fill-plating layer by performing fill-plating on the entire surface of the substrate in which the hole is formed, forming an insulating film layer on the other surface of the substrate, and performing an etching process on one surface and the other surface of the substrate.

Abstract translation: 本发明公开了一种印刷电路板及其制造方法。 印刷电路板的制造方法包括：在形成在基底基板的一个表面上的金属层上形成第一电路图案; 在层叠嵌有第一电路图案的第一绝缘层之后形成第二电路图案; 在第二电路图案上依次层叠第二绝缘层和初步第三电路图案; 分离基底并在分离的基底中形成孔; 以及通过在其上形成孔的基板的整个表面上进行填充镀敷形成第三电路图案，无地形第一填充镀层和第二填充镀层，在另一表面上形成绝缘膜层 并且在基板的一个表面和另一个表面上进行蚀刻处理。

公开(公告)号：US08302298B2

公开(公告)日：2012-11-06

申请号：US12835085

申请日：2010-07-13

Applicant: Chen-Yueh Kung ,  Wei-Cheng Chen

Inventor： Chen-Yueh Kung ,  Wei-Cheng Chen

IPC: H01K3/10

CPC classification number: H05K3/4007 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for fabricating a circuit substrate is provided. A patterned conductive layer having an inner pad is provided on a base layer, a dielectric layer is disposed on the base layer and covers the patterned conductive layer, and a covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second opening is formed. Finally, the patterned mask, surplus layer and covering layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 具有内垫的图案化导电层设置在基底层上，电介质层设置在基底层上并覆盖图案化的导电层，并且覆盖层设置在电介质层上。 通过干蚀刻去除覆盖层的一部分以形成第一开口。 去除由第一开口暴露的电介质层的一部分，以形成暴露一部分内垫的电介质开口。 在覆盖层上形成具有第二开口以露出内部衬垫的一部分的图案化掩模。 形成包括填充电介质开口的导电块，填充第一开口的外垫和填充第二开口的剩余层的导电结构。 最后，去除图案化掩模，剩余层和覆盖层。

公开(公告)号：US20120267155A1

公开(公告)日：2012-10-25

申请号：US13543547

申请日：2012-07-06

Applicant: Chen-Yueh Kung

Inventor： Chen-Yueh Kung

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/0361 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1152 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit substrate includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block.

Abstract translation: 电路基板包括基底层，图案化导电层，电介质层，外部焊盘和导电块。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 外垫设置在电介质层上。 导电层通过电介质层并连接在外焊盘和内焊盘之间，其中外焊盘和导电块形成为整体单元，外焊盘的外径基本上等于外焊盘 的导电块。

公开(公告)号：US08024856B2

公开(公告)日：2011-09-27

申请号：US12010197

申请日：2008-01-22

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/423 ,  H05K1/116 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1152 ,  Y10S205/92 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.

Abstract translation: 公开了一种制造印刷电路板的方法。 一种制造印刷电路板的方法，包括：在第一载体上形成至少一个层间连接器，在第一载体上堆叠至少一个绝缘层，使得层间连接器暴露，去除第一载体，至少形成 绝缘层上的一个电路图案使得电路图案与层间连接器电耦合，可以用于增加电路图案的密度，因为该方法可以在不使用焊盘的情况下提供电路图案和通孔之间的电连接。

公开(公告)号：US20090260868A1

公开(公告)日：2009-10-22

申请号：US12215413

申请日：2008-06-27

Applicant: Chang Gun Oh ,  Mi Sun Hwang ,  Suk Won Lee

Inventor： Chang Gun Oh ,  Mi Sun Hwang ,  Suk Won Lee

IPC: H05K1/00 ,  H05K3/42

CPC classification number: H05K3/4647 ,  H05K3/108 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2203/0574 ,  H05K2203/0733 ,  Y10T29/49165

Abstract: The printed circuit board includes the via formed with the electroplating layer unlike a conventional via formed with an electroless plating layer and an electroplating layer and having a cylindrical shape, and thus exhibits good interlayer electrical connection and high reliability of physical contact upon thermal stress caused by the variance in physical properties of material depending on changes in temperature. The via has no upper land, and thus a fine circuit pattern of the circuit layer can be formed on the via.

Abstract translation: 印刷电路板包括形成有电镀层的通孔，与通过形成有化学镀层和电镀层并且具有圆柱形状的常规通孔不同，由此表现出良好的层间电连接和由于热应力引起的物理接触的高可靠性 材料的物理性质随温度变化的变化。 通孔没有上部焊盘，因此可以在通孔上形成电路层的精细电路图案。