公开(公告)号：EP1742257B1

公开(公告)日：2012-09-05

申请号：EP05425483.4

申请日：2005-07-08

Applicant: STMicroelectronics Srl

Inventor： Arena, Giuseppe ,  Donato, Caterina ,  Camalleri, Cateno Marco ,  Magri', Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

公开(公告)号：EP2466629A2

公开(公告)日：2012-06-20

申请号：EP11193548.2

申请日：2011-12-14

Applicant: STMicroelectronics Srl

Inventor： Borzi, Anna ,  Coccorese, Corrado ,  Morale, Giuseppe ,  Repici, Domenico

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/31658 ,  H01L21/32105 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising: forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region by depositing a first silicon containing layer provided with an increased oxidation rate relatively to an exposed surface of said crystalline semiconductor region in said cavity and depositing a second silicon containing layer above said silicon containing layer with a different oxidation rate relatively to said silicon containing layer, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer, concurrently oxidizing said exposed surface of said crystalline semiconductor region in said cavity and an exposed surface of said first semiconductor electrode so as to form a first oxide layer on said exposed surface of said first semiconductor electrode and a second oxide layer on said exposed surface of said crystalline semiconductor region and forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically isolated from said first semiconductor electrode by said first oxide layer.

公开(公告)号：EP2466486A1

公开(公告)日：2012-06-20

申请号：EP10425386.9

申请日：2010-12-16

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Srl

Inventor： Urzi, Ignazio Antonino ,  D'Audigier, Philippe ,  Mangano, Daniele

IPC: G06F15/78

CPC classification number: G06F15/7842 ,  G06F15/7825

Abstract: An arrangement comprising a node having a node input configured to receive a plurality of transactions intended for a plurality of different targets, said node having a plurality of node outputs; at least one target, said at least one target comprising an input configured to receive a respective output of said node; an output, wherein said node is configured to direct said transactions to one of said at least one target and said output depending on if said transactions are intended for said at least one target or at least one different target.

Abstract translation: 包括具有节点输入的节点的配置，所述节点输入被配置为接收旨在用于多个不同目标的多个事务，所述节点具有多个节点输出; 所述至少一个目标包括被配置为接收所述节点的相应输出的输入; 输出，其中所述节点被配置为根据所述事务是否打算用于所述至少一个目标或至少一个不同目标，将所述事务导向所述至少一个目标和所述输出中的一个。

公开(公告)号：EP2466451A1

公开(公告)日：2012-06-20

申请号：EP11192081.5

申请日：2011-12-06

Applicant: STMicroelectronics Srl

Inventor： Dondini, Mirko ,  Nastasi, Cristina

IPC: G06F5/08

CPC classification number: G06F5/08

Abstract: Operation of a memory with a plurality of locations (101, 102, 103), such as a FIFO buffer memory envisages:
- writing the data (D1, D2) at input to the memory in a single write location (101); and
- making the single write location (101) available for writing an input datum (D1, D2) with a shift of the datum written in the single write location (101) to another location (102) of the memory.
At each operation of writing of an input datum (D1, D2) in the single write location (101), there is scheduled shifting of the datum written therein to another location (102), without waiting for a new write request, thus eliminating the combinational constraint between the two operations.

Abstract translation: 具有诸如FIFO缓冲存储器的多个位置（101,102,103）的存储器的操作设想： - 在单个写入位置（101）中将数据（D1，D2）输入到存储器中; 以及 - 使所述单个写入位置（101）可用于以写入所述单个写入位置（101）的所述基准的移位写入所述存储器的另一位置（102）来写入输入数据（D1，D2）。 在单个写入位置（101）中对输入数据（D1，D2）进行写入的每个操作时，在其中写入的数据被调度到另一个位置（102），而不需要等待新的写入请求，从而消除 两个操作之间的组合约束。

公开(公告)号：EP2458529A1

公开(公告)日：2012-05-30

申请号：EP11191126.9

申请日：2011-11-29

Applicant: STMicroelectronics Srl

Inventor： La Rosa, Manuela ,  Patti, Davide Giuseppe

IPC: G06K19/07 ,  G06K19/077

CPC classification number: G06K19/07749 ,  G06K19/0723 ,  Y10T29/49018

Abstract: A self consistent monitoring device comprises a core cell wirelessly RF identifiable and excitable comprising a tag antenna adapted to exchange data with a data acquisition reader device via electromagnetic or magnetic coupling of the tag antenna with an antenna of the reader device, a monolithically integrated circuit including al least a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit, a detection circuit, logic and/or analog signal processing circuit, and at least a one tier corolla of identical or different sensor cells around said core cell, covering an area of a monitored structure or body onto which the multi-cellular monitoring device is applied that is a multiple of the individual surface area of a single sensor cell, all sensor cells adapted to convert a change of a geometrical, physical, or chemical parameter or state at the cell location, parameter change and location being detected by the detection circuit of the core cell, upon excitation by said reader device.
Generally, the self consistent monitoring device constitutes a unitary module that is replicated innumerable times over a flexible supporting cloth or plastic film, forming a bi-dimensional tablecloth array of identical or different monitoring devices each covering a certain surface area of a monitored structure or body.

Abstract translation: 自我一致的监测装置包括无线RF可识别和可兴奋的核心小区，包括适于通过标签天线与读取装置的天线的电磁或磁耦合与数据采集读取装置交换数据的标签天线，包括 至少一个谐振电容器，调制器，整流器电路，电荷泵电路，检测电路，逻辑和/或模拟信号处理电路以及围绕所述核心单元的相同或不同传感器单元的至少一层花冠， 覆盖被应用多监视结构或身体的区域，多单元监视设备被应用于单个传感器单元的单独表面积的倍数，适于转换几何，物理或化学的变化的所有传感器单元 在单元位置的参数或状态，由核心单元的检测电路检测到的参数改变和位置，在被s激励时 辅助阅读器设备。 通常，自我一致的监测装置构成在柔性支撑布或塑料薄膜上无数次复制的单一模块，形成相同或不同监测装置的二维桌布阵列，每个监视装置覆盖被监测结构或身体的某一表面积 。

公开(公告)号：EP1416720B1

公开(公告)日：2012-05-09

申请号：EP02425655.4

申请日：2002-10-29

Applicant: STMicroelectronics Srl

Inventor： Pappalardo, Francesco ,  Capra, Alessandro ,  Mancuso, Massimo ,  Broquin, Hervé ,  Foderà, Paolo Antonino ,  Salurso, Elena

IPC: H04N1/64

CPC classification number: H04N1/648

公开(公告)号：EP2204860B1

公开(公告)日：2012-02-08

申请号：EP09180915.2

申请日：2009-12-29

Applicant: STMicroelectronics Srl

Inventor： Lee, Jinwook ,  Chang, Kuo-wei ,  Reid, Jason S. ,  Deweerd, Wim Y. ,  Diaz, Aleshandre M.

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2427 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1641 ,  H01L45/1683 ,  Y10S438/90

公开(公告)号：EP0833393B1

公开(公告)日：2011-12-14

申请号：EP96830493.1

申请日：1996-09-30

Applicant: STMicroelectronics Srl

Inventor： Cappelletti, Paolo

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/49 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518

公开(公告)号：EP1630881B1

公开(公告)日：2011-11-16

申请号：EP04425648.5

申请日：2004-08-31

Applicant: STMicroelectronics Srl

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco ,  Rizzotto, Gianguido

IPC: H01L51/00 ,  H01L51/40 ,  G11C13/02

CPC classification number: H01L51/0021 ,  G11C2213/77 ,  H01L27/285 ,  H01L51/0595 ,  Y10S257/90 ,  Y10S977/712 ,  Y10S977/72 ,  Y10S977/722 ,  Y10S977/723

公开(公告)号：EP2273543A3

公开(公告)日：2011-10-26

申请号：EP10183287.1

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of copper, or alloys thereof; and an upper layer. Advantageously, the upper layer consists of:
a first film (9) of nickel or alloys thereof, overlying the lower layer (7) of copper or alloys thereof; and
a second film (10) of gold or alloys thereof, overlying the first film (9) of nickel or alloys thereof.
Moreover, the layer (7) or film (9, 10) are deposited by an electroless chemical process.

Abstract translation: 本发明公开了一种半导体电子器件（1），其包括半导体材料管芯（2）和支撑件（3），半导体材料管芯（2）包括集成电子电路和多个关联焊盘（6） 所述多个接触焊盘（6）中的每一个接触焊盘包括铜或其合金的下层（7）;其中所述电子电路通过导线（4）电连接到所述支撑件（3） 和上层。 有利的是，上层由以下部分组成：第一层镍或其合金薄膜（9），覆盖在铜或其合金的下层（7）上; 和覆盖镍或其合金的第一膜（9）的第二层金或其合金薄膜（10）。 此外，通过无电化学处理来沉积层（7）或膜（9,10）。