公开(公告)号：WO0002081A3

公开(公告)日：2000-04-20

申请号：PCT/US9914679

申请日：1999-06-29

Applicant: CANDESCENT TECH CORP

Inventor： SCHROPP DONALD R JR ,  FIELD JOHN E ,  DUNPHY JAMES C ,  PAN LAWRENCE S ,  MORRIS DAVID L ,  BESSER RONALD S ,  SPINDT CHRISTOPHER J

IPC: H01J29/04 ,  H01J29/02 ,  H01J29/32 ,  H01J29/48 ,  H01J29/62 ,  H01J29/87 ,  H01J31/12 ,  H01J19/38

CPC classification number: H01J29/028 ,  H01J29/467 ,  H01J29/481 ,  H01J31/127 ,  H01J2201/025 ,  H01J2329/8625

Abstract: The intensity at which electrons emitted by a first plate structure (10) in a slat-panel display strike a second plate structure (12) for causing it to emit light is controlled so as to reduce image degradation that could otherwise arise from undesired electron-trajectory changes caused by effects such as the presence of a spacer system (14) between the plate structures. An electron-emissive region (20) in the first plate structure typically contains multiple laterally separated electron-emissive portions (201 and 202) for selectively emitting electrons. An electron-focusing system in the first plate structure has corresponding focus openings (40p1 and 40p2) through which electrons emitted by the electron-emissive portions respectively pass. Upon being struck by the so-emitted electrons, a light-emissive region (22) in the second plate structure emits light to produce at least part of a dot of the display's image.

Abstract translation: 通过板条显示器中的第一板结构（10）发射的电子撞击第二板结构（12）以使其发射光的强度被控制，以便减少否则可能由不希望的电子 - 由诸如在板结构之间存在间隔系统（14）的效应引起的轨迹变化。 第一板结构中的电子发射区域（20）通常包含多个横向分离的电子发射部分（201和202），用于选择性地发射电子。 第一板结构中的电子聚焦系统具有对应的聚焦开口（40p1和40p2），由电子发射部分发射的电子分别通过聚焦开口（40p1和40p2）。 在被如此发射的电子撞击时，第二板结构中的发光区域（22）发光以产生显示器图像的点的至少一部分。

公开(公告)号：WO9849708A3

公开(公告)日：1999-03-18

申请号：PCT/US9807633

申请日：1998-04-27

Applicant: CANDESCENT TECH CORP

Inventor： HAVEN DUANE A ,  LEARN ARTHUR J ,  PORTER JOHN D

IPC: G03F7/20 ,  H01J9/227 ,  H01J29/08 ,  H01J29/32 ,  H01J29/87 ,  H01J31/12 ,  H01J29/10

CPC classification number: H01J29/085 ,  H01J31/127

Abstract: Openings are created in a structure by a process in which a plate (20) is furnished with a sacrificial patterned masking layer divided into multiple laterally separated mask portions (22A). A primary layer of actinic material (28) is provided over the masking layer and in the space between the mask portions. Material of the primary layer that is not shadowed by a mask formed with the mask portions is backside exposed to actinic radiation (30). Material of the primary layer not exposed to the radiation is removed. Segments of the masking layer not covered by exposed material of the primary layer are then removed. Consequently, openings extend through the primary layer where the segments of the masking layer have been removed. The process is typically employed in forming an optical device such as a flat-panel cathode-ray tube display in which the openings in the primary layer receive light-emissive material.

公开(公告)号：WO2004049370A3

公开(公告)日：2004-10-07

申请号：PCT/US0340050

申请日：2003-11-19

Applicant: CANDESCENT TECH CORP

Inventor： GAGANAM MADHUKAR ,  RAO KRISHNA A ,  DANIELSON DON L

IPC: G09G3/22 ,  G09G3/10 ,  G09G5/10 ,  H01J1/62 ,  H01J63/04

CPC classification number: G09G3/22 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/0666 ,  G09G2320/0686

Abstract: A present invention field emission display brightness compensation system and method is capable of providing uniform display correction. In one present compensation system and method a masking process is utilized that adjusts the emissions for a particular area (330, 350, 370, 390). In one exemplary implementation, the relative value of a pixel driver voltage is adjusted to correspond to a base brightness area. For example, an emitter uniformity area adjustment table is utilized to adjust the voltage value of the emitters. In emitter uniformity area adjustment table provides a correlation between a pixel location and a brightness level adjustment. The emitter uniformity area adjustment tables are utilized to create a software filtering mask that provides compensation for uniformity differences between different spots or areas in the display.

Abstract translation: 本发明的场发射显示亮度补偿系统和方法能够提供均匀的显示校正。 在一种现有的补偿系统和方法中，利用调整特定区域（330,350,370,390）的排放的掩蔽过程。 在一个示例性实现中，调整像素驱动器电压的相对值以对应于基本亮度区域。 例如，使用发射极均匀性区域调整表来调整发射体的电压值。 在发射极均匀性区域调整表提供像素位置和亮度水平调整之间的相关性。 发射器均匀性区域调整表用于创建软件滤波掩模，其提供对显示器中不同点或区域之间的均匀性差异的补偿。

公开(公告)号：WO03015118A3

公开(公告)日：2003-04-24

申请号：PCT/US0224462

申请日：2002-08-02

Applicant: CANDESCENT TECH CORP

Inventor： LEE JUENG-GIL ,  FAHLEN THEODORE S

IPC: H01J9/26 ,  H01J9/32 ,  H01J9/00

CPC classification number: H01J9/32 ,  H01J9/261 ,  H01J2209/268

Abstract: A method for attaching a faceplate and a backplate (205) of a field emission display device (200). Specifically, one embodiment of the present invention discloses a method for protecting a silicon nitride passivation layer (290) from reacting with a glass seal sealing material (260) that contains lead oxide during an oven sealing or laser sealing process (350). The passivation layer (290) protects row and column electrodes (220, 230) in the display device (200). A barrier material (280) fully encapsulates the silicon nitride passivation layer (290). In one embodiment, silicon dioxide is the barrier material (280). In another embodiment, spin-on-glass is the barrier material (280). In still another embodiment, cermet is the barrier material (280).

Abstract translation: 一种用于附接场致发射显示设备（200）的面板和背板（205）的方法。 具体而言，本发明的一个实施例公开了一种在烘箱密封或激光密封工艺（350）期间保护氮化硅钝化层（290）不与含有氧化铅的玻璃密封密封材料（260）反应的方法。 钝化层（290）保护显示装置（200）中的行和列电极（220,230）。 阻挡材料（280）完全封装氮化硅钝化层（290）。 在一个实施例中，二氧化硅是阻挡材料（280）。 在另一个实施例中，旋涂玻璃是阻挡材料（280）。 在又一个实施例中，金属陶瓷是阻挡材料（280）。

公开(公告)号：WO0210846A3

公开(公告)日：2002-05-16

申请号：PCT/US0123722

申请日：2001-07-26

Applicant: CANDESCENT TECH CORP ,  SONY CORP

Inventor： LUDWIG PAUL N ,  FAHLEN THEODORE S ,  KANAGAWA SHINJI ,  SUN JENNIFER Y

IPC: G02F1/1339 ,  H01J9/26

CPC classification number: H01J9/261 ,  H01J2211/48 ,  H01J2329/867 ,  H01J2329/8675

Abstract: A flat-panel display is hermetically sealed by a process in which a first plate structure (30) is positioned generally opposite a second plate structure (32) such that sealing material (34) provided over the second plate structure lies between the plate structures. In a gravitational sealing technique, the first plate structure is positioned vertically below the second plate structure. The sealing material is heated so that it moves vertically downward under gravitational influence to meet the first plate structure and seal the plate structures together. In a global-heating gap-jumping technique, the plate structures and sealing material are globally heated to cause the sealing material to jump a gap between the sealing material and the first plate structure. When the first plate structure is positioned vertically above the second plate structure, the sealing material moves vertically upward to meet the first plate structure and close the gap.

Abstract translation: 平板显示器通过其中第一板结构（30）大致与第二板结构（32）相对放置的过程而被气密密封，使得设置在第二板结构上的密封材料（34）位于板结构之间。 在重力密封技术中，第一板结构垂直定位在第二板结构下方。 密封材料被加热以使其在重力影响下垂直向下移动以与第一板结构相遇并将板结构密封在一起。 在全局加热间隙跳跃技术中，板结构和密封材料被全面加热以使密封材料跳过密封材料和第一板结构之间的间隙。 当第一板结构垂直定位在第二板结构上方时，密封材料垂直向上移动以接合第一板结构并封闭间隙。

公开(公告)号：WO0013168A9

公开(公告)日：2000-10-05

申请号：PCT/US9915893

申请日：1999-07-14

Applicant: CANDESCENT TECH CORP

Inventor： MASLENNIKOV IGOR L ,  URBON DENNIS M ,  SPINDT CHRISTOPHER J ,  HANSEN RONALD L ,  CURTIN CHRISTOPHER J

IPC: H01J29/04 ,  G09G3/20 ,  G09G3/22 ,  H01J31/12 ,  H04N5/68 ,  G09G3/12

CPC classification number: G09G3/22 ,  G09G3/2011 ,  G09G2310/0267 ,  G09G2310/06 ,  G09G2320/029 ,  G09G2320/043 ,  G09G2330/02 ,  G09G2330/028

Abstract: A field emission display (700) having an improved operational life. In one embodiment, the field emission display (700) comprises a plurality of row lines (230), a plurality of column lines (250), and a plurality of electron emissive elements (40) disposed at intersections of the plurality of row lines (230) and column lines (250), a column driver circuit (740) and a row driver circuit (720). The column driver circuit (740) is coupled to drive column voltage signals over the plurality of column lines (250); and the row driver circuit (720) is coupled to activate and deactivate the plurality of row lines (230) with row voltage signals. According to the present invention, operation life of the field emission display is extended when the electron emissive elements are intermittently reverse-biased by the column voltage signals and the row voltage signals. In another embodiment, the row driver circuit is responsive to a SLEEP signal (770). The row driver circuit (720), upon receiving the SLEEP signal (770), drives a sleep-mode voltage over the row lines (230) to reverse-bias the electron emissive elements.

Abstract translation: 场发射显示器（700）具有改进的操作寿命。 在一个实施例中，场致发射显示器（700）包括多个行线（230），多个列线（250）以及多个电子发射元件（40），所述多个电子发射元件设置在多条行线的交叉点处 230）和列线（250），列驱动器电路（740）和行驱动器电路（720）。 列驱动器电路（740）被耦合以通过多条列线（250）驱动列电压信号; 并且行驱动器电路（720）被耦合以利用行电压信号来激活和去激活多条行线（230）。 根据本发明，当电子发射元件被列电压信号和行电压信号间歇地反向偏置时，场发射显示器的工作寿命延长。 在另一个实施例中，行驱动器电路响应于SLEEP信号（770）。 行驱动器电路（720）在接收到睡眠信号（770）时驱动行线（230）上的睡眠模式电压以反向偏置电子发射元件。

公开(公告)号：EP1029337A4

公开(公告)日：2005-04-06

申请号：EP98936954

申请日：1998-07-21

Applicant: CANDESCENT TECH CORP

Inventor： ELIZONDO PHILIP J ,  CHAKRAVORTY KISHORE K ,  CAUDILLO DAVID

IPC: H01J9/02

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: A method for uniformly depositing polymer particles (800) onto the surface of a gate metal layer during the formation of a gate electrode. In one embodiment, the present invention comprises immersing a substrate (906) having a layer of a gate metal disposed over the surface thereof in a fluid bath (902) containing polymer particles. Additionally, in the present embodiment, the layer of gate metal disposed over the substrate has approximately the same thickness as a desired thickness of the gate electrode to be formed. Next, the present embodiment applies a uniform potential across the surface of the layer of gate metal such that the polymer particles (800) are uniformly deposited onto the layer of gate metal with a spatial density of approximately 100,000,000 to 1,000,000,000,000 particles per square centimeter. In the present embodiment the polymer particles adhere to the surface of the layer of gate metal via Van der Waal's forces and/or via a charge difference between each particle and the layer of gate metal. The present embodiment then removes the substrate having the layer of the gate metal and the particles deposited thereon from the fluid bath.

Abstract translation: 用于聚合物颗粒的均匀沉积到金属栅极的表面上的栅电极的形成过程中的方法。 在一个，在本实施方式本发明包括总是唱具有在流体中的浴，其含有的聚合物颗粒其设置在所述表面上的金属栅极的层的基材。 在此，实施方式中，流体浴被包含在流体浴箱中。 另外，在本实施方式中，设置在基板上的栅极金属的层的厚度大约为所述栅电极的所希望的厚度所形成的相同。 接着，对本实施例应用跨越栅极金属的检查的层的表面均匀的电位做的聚合物粒子均匀地沉积到栅极金属的层。 在这样做时，本实施例的一致沉积在聚合物颗粒到栅金属的层。 另外，在本实施方式中，所述聚合物颗粒附着于通过范德华力和/或经由栅极金属层与各聚合物粒子之间的电荷差的栅极金属层的表面上。 在本实施方式中，所述聚合物颗粒沉积在栅极金属层的表面上每平方厘米1×10 8，大约1×10 -12至粒子的空间密度。 在本实施方式然后移除具有栅极金属的层中的底物和从流体浴沉积在其上的颗粒。

公开(公告)号：EP1038303A4

公开(公告)日：2002-04-24

申请号：EP98956230

申请日：1998-10-27

Applicant: CANDESCENT TECH CORP

Inventor： CLEEVES JAMES M ,  SPINDT CHRISTOPHER J ,  BARTON ROGER W ,  CHAKRAVORTY KISHORE K ,  LEARN ARTHUR J ,  OBERG STEPHANIE J

IPC: H01J9/02 ,  H01J1/304 ,  H01J3/02 ,  H01J29/04 ,  H01J29/46 ,  H01J31/12 ,  H01J1/30

CPC classification number: H01J3/021 ,  H01J1/3042 ,  H01J29/467 ,  H01J2201/319 ,  H01J2329/00

Abstract: An electron-emitting device contains a vertical emitter resistor patterned into multiple laterally separated sections (34, 34V, 46, or 46V) situated between the electron-emissive elements (40), on one hand, and emitter electrodes (32), on the other hand. Sections of the resistor are spaced apart along each emitter electrode. The resistor can be formed in a manner self aligned to control electrodes (38 or 52A/58B) of the device or with a separate resistor mask.

公开(公告)号：EP0975437A4

公开(公告)日：2001-05-09

申请号：EP98913107

申请日：1998-03-25

Applicant: CANDESCENT TECH CORP

Inventor： DRUMM PAUL M

IPC: G03F7/40 ,  G02F1/1335 ,  G03F7/00 ,  G09F9/30 ,  H01J1/74 ,  H01J9/227 ,  H01J29/08 ,  H01J29/32 ,  H01J31/12 ,  B05D5/12 ,  C23C16/00 ,  G03C5/00 ,  G09G3/20 ,  G09G3/30

CPC classification number: H01J29/085 ,  G02F1/133512 ,  G03F7/0035 ,  H01J9/2278 ,  H01J2329/00

Abstract: A method for forming a conductively coated matrix structure for separating rows and columns of sub-pixels (106) on the faceplate (104) of a flat panel display device. One embodiment deposits a photoresistive material (108) over the interior surface (102) of a faceplate having a non-conductive opaque matrix structure (100) formed thereon, and into sub-pixel regions separated by the matrix structure. The photoresistive material is dried and exposed to light (112) in the sub-pixel regions. After unexposed photoresistive material (110) is removed, a layer of aluminum is evaporated onto the interior surface of the faceplate such that the matrix structure and the exposed layer of photoresistive material in the sub-pixel regions is coated with conductive aluminum. Next, an etchant is applied to the exposed photoresistive material disposed in the sub-pixel regions, removing the exposed photoresistive material and the overlying Al layer from the sub-pixel regions, such that the conductive Al layer remains only on the matrix structure, and does not cover the sub-pixel regions.

公开(公告)号：EP0995213A4

公开(公告)日：2001-04-04

申请号：EP98922233

申请日：1998-05-12

Applicant: CANDESCENT TECH CORP

Inventor： CHAKRAVORTY KISHORE K ,  ELIZONDO PHILIP J

IPC: H01J9/02

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: A method for forming a gate electrode comprises depositing a gate metal (604) over an insulating substrate (602) and etching openings in areas of the gate layer which are exposed through a hard mask. The layer of the gate metal (604) is deposited to a thickness approximately the same as the thickness desired for the gate electrode. Next, polymer particles (700) are deposited over the layer of gate metal. A hard mask layer (800) is then deposited over the polymer particles and the layer of gate metal. Then the polymer particles (700) and portions of the hard mask (800) which overlie the polymer particles are removed such that first regions of the gate metal (604) are exposed while second regions remain covered by the hard mask. After openings have been formed completely through the gate metal in the first regions, the remaining portions of the hard mask are removed.

Abstract translation: 一种形成栅电极的方法。 在一个实施例中，本发明包括在下面的衬底上沉积栅极金属，使得栅极金属层形成在下面的衬底之上。 在本发明中，栅极金属层被沉积​​成与栅电极所需厚度大致相同的厚度。 接下来，本发明将聚合物颗粒沉积在栅极金属层上。 然后将硬掩模层沉积在聚合物颗粒和栅极金属层上。 本发明除去聚合物颗粒和覆盖聚合物颗粒的硬掩模层的部分，使得栅极金属层的第一区域暴露，并且使得栅极金属层的第二区域保持被硬的覆盖 掩模层。 在去除步骤之后，本发明通过栅极金属层的第一区域蚀刻，使得开口完全穿过第一区域的栅极金属层形成。 在已经形成开口之后，去除覆盖在栅极金属层的第二区域上的硬掩模层的剩余部分。