公开(公告)号：JP2000196088A

公开(公告)日：2000-07-14

申请号：JP37063799

申请日：1999-12-27

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SENTIRU SURINIVASAN ,  WEYBRIGHT MARY ,  GAMBINO JEFFREY ,  THOMAS RUPP

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/283 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To protect oxidizable material which forms a gate from oxidation by a method wherein an anti-oxidant layer is formed on the gate of a transistor, and the gate with an anti-oxidant layer is exposed to an oxidizing atmosphere to form the source and drain of the transistor. SOLUTION: A gate insulating layer 11 and a gate metal coating layer 13 are laminated on a semiconductor substrate 10, where the coating layer 13 is composed of a doped silicon layer 14 and a tungsten silicide layer 16 deposited on the silicon layer 14. A silicon nitride layer 18 is deposited on the silicide layer 16, and a mask 30 with an opening 31 is provided on the silicon nitride layer 18 and the gate metal coating layer 13. Thereafter, a gate G of a transistor is formed in a region masked with the mask 30 by plasma etching, An anti-oxidant layer 32 is formed on the side walls of the gate G, the silicon nitride layer 18, and the doped silicon layer 14, and the gate G is exposed to an oxidizing atmosphere for the formation of a source region S and a drain region D.

公开(公告)号：JP2000195791A

公开(公告)日：2000-07-14

申请号：JP37548699

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： CHIIAN RUU ,  SHAOMIN IN

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/11

Abstract: PROBLEM TO BE SOLVED: To improve the control of important dimensions by depositing a multilayer ARC laminate layer which combines the absorption and diminishing interference modes together. SOLUTION: An antireflective coat(ARC) layer 130 is formed on a substrate 110. This layer is a multilayer ARC layer composed of a first and second ARC layers 135, 140. The second ARC layer 140 is deposited on the first ARC layer 135 which is deposited on the substrate 110. A resist 170 is formed on the second ARC layer wherein the first ARC layer operates in the absorption mode and the second ARC layer operates in the diminishing interference mode, the refractive index of the second ARC layer is selected so as to minimize the reflection on the resist, the first ARC layer 135 has an adequate extinction coefficient k and wall thickness for absorbing lights and the coefficient k is about 0.2 or more, pref. 0.5 or more.

公开(公告)号：JP2002270700A

公开(公告)日：2002-09-20

申请号：JP2002002654

申请日：2002-01-09

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NESBIT LARRY A ,  FALTERMEIER JOHNATHAN E ,  RAMACHANDORA DEIVAKARUNI ,  BERGNER WOLFGANG

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a bit-line contact and formation method thereof for a vertical DRAM array, using a bit-line contact mask. SOLUTION: In this method, a gate conductor line is formed. An oxide layer 35 is adhered to the gate conductor line, and a bit-line contact mask 40 is formed on a part of the oxide layer 35. The bit-line contact mask 40 is etched, and a silicon layer 45 is made to stick on a substrate 5. A bit-line layer 50 is adhered to the silicon layer 45. Masking and etching processes are carried out with a bit-line layer 50. An M0 metal 60 is made to adhere to the silicon layer 45, as well as on both sides of non-etching part of the bit-line (M0) layer 50, and forms the left and right bit lines.

公开(公告)号：JP2002026733A

公开(公告)日：2002-01-25

申请号：JP2000172486

申请日：2000-06-08

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TOOSKY ZABIH

IPC: H03M1/84

Abstract: PROBLEM TO BE SOLVED: To solve the problems that conventionally a digital/analog conversion system that does not satisfy requirements, such that nonlinear transmission characteristics, is required in some applications even though the transmission characteristics of the digital/analog converter is normally linear; data compression is required, when a signal quantity is large and no data compression is required in other signals in some cases; and an integrated circuit providing a nonlinear transmission characteristics of the digital/analog converter is required. SOLUTION: This invention relates to digital/analog conversion. According to one embodiment of this invention, a logarithmic transform characteristics can be generated, by subtracting a fraction of an output current from a reference current according to a recursive expression.

公开(公告)号：JP2001085637A

公开(公告)日：2001-03-30

申请号：JP2000245911

申请日：2000-08-14

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： FURUKAWA TOSHIHARU ,  GRUENING ULRIKE ,  HORAK DAVID V ,  MANDELMAN JACK A ,  RADENS CARL J ,  RUPP THOMAS S

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain a vertical DRAM having a self-aligned word line conductor on the sidewall of a trench by forming a word line conductor having a sidewall aligned with the sidewall of the trench. SOLUTION: A pad nitride is removed selectively depending on the oxide 240 in an STI region 228. A screen oxide is then grown and array region p-well implantation is carried out and an N+ dopant is implanted in order to form a second diffusion region 210. Subsequently, source and drain implantation is carried out in a support region in order to form a diffusion region 288 and an oxide 242 is formed on the sidewalls 219, 233 of a word line conductor 218, 232 and on the sidewall of a support gate. Finally, a bit line conductor 244 of polysilicon is deposited for planarization. Since word line resistance is decreased, a DRAM device having improved performance can be obtained.

公开(公告)号：JP2001015474A

公开(公告)日：2001-01-19

申请号：JP2000153650

申请日：2000-05-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUDELKA STEPHAN ,  RATH DAVID

IPC: B08B3/08 ,  B08B3/10 ,  B08B3/12 ,  H01L21/00 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To avoid the inefficient excessive saturation of heated demineralized water with gas by adjusting the gas concentration in the demineralized water before the water is heated to a selective cleaning temperature for cleaning a semiconductor wafer under ultrasonic vibrating actions. SOLUTION: The gas space in a degassing chamber 11 is maintained at a selective negative pressure by operating a vacuum pump 16 in connection with a pressure sensor 18. Then the pressure in the chamber 11 is adjusted by releasing a selective amount of nitrogen gas from the water in the water space of the chamber 11 to the gas space of the chamber 11 through a chamber thin film, and removing the gas by sucking and exhaling the gas through a gas discharge pipe 17. In addition, the demineralized water in a heating vessel 12 is selectively warmed by means of a controller 21 and supplied to a cleaning tank 13 for ultrasonically cleaning a semiconductor wafer.

公开(公告)号：JP2001005660A

公开(公告)日：2001-01-12

申请号：JP2000157106

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  MATTELA VENKAT ,  CHESTERS ERIC ,  FLECK ROD G

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To make increasable the instruction issue bus bandwidth without increasing the size of a cache memory by selectively storing instructions in the cache memory related to a corresponding function unit. SOLUTION: A 1st instruction is fetched from a memory and it is judged whether its PS matches with one of entries of a tag PC cache (S502, 504). When the tag PC of the fetched instruction matches with one of the entries of one of tag PC caches, the PC of the fetched instruction is updated into a matching target PC specified in a cache memory (S504, 514). When a target instruction is stored in the fetched instruction, the target instruction is fetched from a program memory (S516, 518), but when the target instruction is stored in the fetched instruction, the target instruction is not requested of a programming memory; and a target operation code is injected into a target function unit (S520) in either case together with the target instruction.

公开(公告)号：JP2000357963A

公开(公告)日：2000-12-26

申请号：JP2000118392

申请日：2000-04-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DORTU JEAN-MARC ,  CHU ALBERT M ,  FERRAIOLO FRANK

IPC: G06F1/10 ,  H03K5/14 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081

Abstract: PROBLEM TO BE SOLVED: To obtain a delay element including a delay locked loop(DLL), where a follow-up ability with respect to delay which occurs in a circuit is improved. SOLUTION: A delay locked loop circuit 100 is provided with a delay line 112, the delay element 110 and a phase comparator 114. In this case, the circuit is constituted, in such a way that the delay line 112 generates delay in accordance with a control signal and is connected to an input node and an output node, that the delay element 110 is connected to the input node, gives a prescribed delay value to an input signal from the input node and supplied the delayed input signal is supplied and that the phase comparator 114 is connected to the output node and the delay element 110, compares the phase of the output signal with that of the delayed input signal, and outputs the control signal to the delay line 112 so that the line 112 gives the prescribed delay value to a part between the input node and the output node by the control signal.

公开(公告)号：JP2000338197A

公开(公告)日：2000-12-08

申请号：JP2000095079

申请日：2000-03-30

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GERD FRANKOVSKI ,  TERLETZKI HARTMUD

IPC: G01R31/28 ,  G01R29/027 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3193 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To execute a high resolution test by using an inexpensive tester of comparatively low frequency by mounting a plurality of delay elements capable of being enabled and disabled by pulses from an operation circuit, and the like. SOLUTION: A semiconductor circuit 12 is formed on a single crystalline such as silicon or a substrate 16 (that is, die or chip), and has a plurality of pins 181-18n. These pins 181-18n are connected to a tester 14 through lines 201-20n to be communicated with the tester 14. The tester 14 transmits a signal to the circuit 12, further receives the signal from the circuit 12 and processes the signal. The circuit 12 has an operation circuit 22 and a test circuit 24. The operation circuit 22 generates pulses of very short width. The test circuit 24 has a plurality of delay elements, and these delay elements are enabled and disabled by pulses from the operation circuit 22. By applying this device, the quality of high frequency of the signal of the circuit is measured by a low frequency test device.

公开(公告)号：JP2000277708A

公开(公告)日：2000-10-06

申请号：JP2000073717

申请日：2000-03-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK A ,  NESBIT LARRY ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To prevent resistance of an embedded strap of a DRAM cell from changing by the overlapping manner of a deep trench and an active region. SOLUTION: This semiconductor device contains a semiconductor substrate. At least a pair of deep trenches are formed in the substrate. A collar is formed in at least a part of the sidewall of each of the deep trenches. The inside of each of the deep trenches is filled with a trench filler 44. An embedded strap 46 is formed over the whole of each of the deep trenches and covers the upper surfaces of the trench filler 44 and the collar. An insulating region is formed between a a pair of the deep trenches. A trench upper part dielectric region 52 formed in the deep trench, so as to overlap with the embedded strap 46 of each of the deep trenches.