公开(公告)号：JP2000216373A

公开(公告)日：2000-08-04

申请号：JP1231199

申请日：1999-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KENTEI ,  CHIN SHINRAI ,  SHU SHIBUN

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To prevent generation of gate-drain capacitance by implanting ions into a substrate using a second spacer, offset spacer and a gate structure as a mask thereby forming a source/drain region. SOLUTION: An offset spacer 308 having a thickness 311 is formed on the sidewall of a gate structure and first ion implantation processing 312 for implanting ions into a substrate using the gate structure 302 and an offset spacer 308 as a mask is carried out to obtain an LDD(low doping drain) region 314. Subsequently, a second spacer 316 is formed on the outer sidewall of the offset spacer 308 and second ion implantation processing 322 for implanting ions into the substrate 300 using the second spacer 316 and the gate structure 302 as a mask is carried out to form a source-drain region 318 in the LDD region 314.

公开(公告)号：JP2000216157A

公开(公告)日：2000-08-04

申请号：JP938099

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： GO KONRIN ,  TSAI MENG JIN

IPC: H01L21/3205 ,  H01L21/306

Abstract: PROBLEM TO BE SOLVED: To restrain fine marks caused by excessive polishing or a polishing agent from being formed on a semiconductor substrate, by a method wherein a first insulating film is formed on a semiconductor substrate and metal wires, a second insulating film is formed on the first insulating film, the surface of the second insulating film is polished, and then a thin cap film is formed on the second insulating film. SOLUTION: An inner insulating layer (ILD) 42 is formed on substrate 40, and metal wires 44 are formed on the ILD layer 42. Thereafter, a metal layer is patterned into metal wires. Then, when an insulating layer 46 and an intra- metal layer insulating layer (IMD) 50 are formed on the ILD layer 42 and the metal wires 44, cross sectional structures 48 each shaped like a pyramid are formed above the metal wires 44. Then, the surface of IMD layer 50 is polished through a chemical mechanical polishing method, and a cap layer is formed on the IMD layer 50 so as to cover fine marks 52a and 52b. The cap layer is formed as thick as 1000 to 3000Å and can be formed of silicon dioxide or phospho-silicate glass.

公开(公告)号：JP2000214573A

公开(公告)日：2000-08-04

申请号：JP937999

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN SHIMIN

IPC: H01L21/302 ,  G03F1/76 ,  G03F1/78 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To simultaneously manufacture patterns on both sides of a photomask by installing two sets of pattern forming devices for each on both sides of a masking plate. SOLUTION: A both-side photomask production system consists of a first particle source, a second particle source, a first focusing assembly 200a, a second focusing assembly 200b and a mechanical stage. The mechanical stage is used to mount a masking plate 240 and to move a substrate 242 to a prescribed position. The first and second particle sources are the electron beams generated by an electron gun. The first focusing assembly 200a and the second focusing assembly 200b act simultaneously to respectively converge the two electronic beams onto photoresist layers 248a and 248b. Then, the patterns on the photoresist layers 248a and 248b are transferred to antireflection layers 246a and 246b and masking layers 244a and 244b, by which the both-side photomask are formed.

公开(公告)号：JP2000196079A

公开(公告)日：2000-07-14

申请号：JP37425998

申请日：1998-12-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  RIN KENTEI ,  SHU SHIBUN

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L29/10

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a modified MOS semiconductor suitable for a high level integrated element. SOLUTION: This manufacturing method of a MOS semiconductor includes forming a gate 306 on a substrate 300. The extended source/drain 310a are made on a substrate in the vicinity of the gate. Ion implantation process for implanting heavily impurities which are low in diffusion coefficient within a substrate is carried out. A halogen region which is heavily doped is made under the extended source/drain 310a on the substrate 300. An oblique halogen implantation process is carried out to form a halogen implantation region under the gate, on the side of the extension source/drain region 310a on the substrate 300.

公开(公告)号：JP2000174022A

公开(公告)日：2000-06-23

申请号：JP34587998

申请日：1998-12-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN KATEI ,  O SHITETSU

IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To form an alignment mark of good functional quality for fully utilizing alignment performance by forming a metallic wiring layer, having openings for the mark with a higher step height. SOLUTION: A polysilicon layer 302 is formed on a semiconductor substrate, and a central part of the polysilicon layer is removed to cause the substrate to be exposed. An oxide layer 306 is then formed on the substrate and is patterned to form openings 308 to expose the substrate. A W (tungsten) layer 314 is deposited on the substrate and is flattened with a WCMP (tungsten chemical-mechanical polishing) process to form W plugs 312 in the openings. A metallic wiring layer is formed on the substrate. Finally, an alignment mark pattern is formed in the metallic wiring layer.

公开(公告)号：JP2000058828A

公开(公告)日：2000-02-25

申请号：JP26791898

申请日：1998-09-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUKIN ,  RO GYOREI ,  YEW TRI-RUNG

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide metallic silicide and a method for forming it. SOLUTION: In a silicon substrate 20, a field separation part is given and MOS containing a gate 22, spacers 25 on the side walls of the gate 22, and source/drain areas 24 is installed. A titanium layer 28 is formed on the silicon substrate 20. A first speedy thermal treatment is executed and the titanium layer 28 changes into titanium silicide in a first form. The titanium layer which is not changed into titanium silicide is removed. A high compressible film is formed on the silicon substrate 20. A second speedy thermal treatment is executed and a titanium silicide layer changes to a second form.

公开(公告)号：JP2000036541A

公开(公告)日：2000-02-02

申请号：JP28135498

申请日：1998-10-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHA CHOKEI ,  WOO SHUNGEN ,  RO KATETSU

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285

Abstract: PROBLEM TO BE SOLVED: To prevent a deviation or the like of a pattern in a photolithography or the like by vapor-depositing an intermetallic dielectric layer, patterning a via hole, then forming a titanium layer on the dielectric layer to connect a first aluminum layer formed in the hole, and forming a second aluminum layer on the titanium layer. SOLUTION: A first metal layer 202 is formed on a substrate 200, and then an intermetallic dielectric layer 204 is vapor deposited on the substrate 200 via a CVD. Then, the layer 204 is etched by using a photoresist pattern until a surface of the layer 202 is exposed to form a via hole 208. a second aluminum layer 211 is vapor deposited in the hole 208, and an aluminum via hole 213 is formed. Thereafter, a titanium layer 214 is formed on the layer 204 and the hole 213 by a physical vapor deposition method. A second aluminum layer 216 is formed on the layer 214 by using a physical vapor deposition method.

公开(公告)号：JP2000021879A

公开(公告)日：2000-01-21

申请号：JP31315898

申请日：1998-11-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： HUANG YIMIN ,  YANG MING-SHENG ,  YEW TRI-RUNG

IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To avoid excessively polishing a metal line which would increase the resistance of metal lines and the parasitic capacitance between conductor lines by forming a double waveform pattern, using shallow dummy metal lines. SOLUTION: A thin adhesive layer 328 is formed in shallow metal line trenches and on the surface of an inter-metal dielectric layer 317 along the side walls and bottoms of second metal line trenches, vias, and third metal line trenches, a metal layer and adhesive layer 328 located higher than the inter-metal dielectric layer 317 are polished by the chemical-mechanical polishing to result in that metal layer filled in the second metal line trenches, third metal line trenches 326 and shallow dummy metal line trenches have the same height as the inter-metal dielectric layer 317, thereby avoiding excessively polishing the metal lines which would increase the resistance and hence the operation speed of the device not becomes low because of a small parasitic capacitance.

公开(公告)号：JP2000019714A

公开(公告)日：2000-01-21

申请号：JP25786098

申请日：1998-09-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： BENJAMIN ZU MIN RIN

IPC: H01L21/027 ,  G03F1/32 ,  G03F1/42 ,  G03F1/68 ,  G03F9/00 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a phase shift mask capable of performing accurate mask alignment. SOLUTION: A phase shift mask for shifting a phase has a transparent substrate having a first surface and second surface, a first pattern layer provided on the first surface of the transparent substrate for forming a mark pattern for aligning the phase shift mask by exposing a part of the first surface, and a second pattern layer provided on the second surface of the transparent substrate for covering the mark pattern so as to cover rays of light passing through the mark pattern by forming a hole pattern for manufacture by exposing a part of the second surface. Preferably, the transparent substrate has quartz or glass. The first pattern layer has a material that cuts off light, such as chromium. The second pattern layer has a material capable of shifting the phase of light, for example, by 180 degrees. The second pattern layer has transmissivity of about 3% to 10% while a pattern of the second pattern layer is being changed, and has transmissivity of about 50% while the phase shift mask is being aligned.

公开(公告)号：JPH11330077A

公开(公告)日：1999-11-30

申请号：JP18624498

申请日：1998-07-01

Applicant: UNITED MICROELECTRONICS CORP

Inventor： TSAI MENG JIN

IPC: H01L21/302 ,  H01L21/027 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide, in a simple process, dual damasking technology for forming dual damask structure without the occurrence of misalignments. SOLUTION: The forming technology of dual damask structure contains a process for forming an oxide layer 56 and a mask layer 58 on the oxide layer 56. The oxide layer 56 and the mask layer 58 have projections 57 positioned above first conduction layers 54. Chemical-mechanical polishing is executed, and the projections are removed. Then, an opening 59 is formed. A second conductive layer 68 is formed in the opening 59, and the second conductive layer 68 is brought into contact with the first conductive layer 54.