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公开(公告)号：KR1020130036697A
公开(公告)日：2013-04-12
申请号：KR1020120052201
申请日：2012-05-16
Applicant: 한국전자통신연구원
IPC: H04L27/18
CPC classification number: H04L27/20
Abstract: PURPOSE: A device for inputting the signal of a digital-RF converter is provided to improve a signal-noise ratio by generating noise generated by the excessive response of an input signal in a specific frequency or a random frequency. CONSTITUTION: A device for inputting the signal of a digital-RF converter(100) includes a phase-modulated signal input unit inputting a phase-modulated transmission signal into the LO switch(130) of the digital-RF converter; and a digital signal input unit modifying a digital signal in order to correspond to the phase-modulated transmission signal and inputting the modified digital signal into the data switch(121,122) of the digital-RF converter.
Abstract translation: 目的：提供用于输入数字RF转换器的信号的装置，用于通过产生由特定频率或随机频率的输入信号的过度响应产生的噪声来提高信噪比。 构成：用于输入数字RF转换器（100）的信号的装置包括相位调制信号输入单元，其将相位调制的发送信号输入到数字RF转换器的LO开关（130）中; 以及数字信号输入单元，其修改数字信号以便对应于相位调制的传输信号，并将修改的数字信号输入到数字RF转换器的数据开关（121,122）中。
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公开(公告)号：KR1020130029346A
公开(公告)日：2013-03-22
申请号：KR1020120101370
申请日：2012-09-13
Applicant: 한국전자통신연구원
IPC: H03D7/00
Abstract: PURPOSE: A programmable demodulation frequency mixer is provided to improve the performance of a transceiver by reducing a process band width of the transceiver, power consumption, and the size of a chip. CONSTITUTION: A programmable demodulation frequency mixer(20) includes an I/Q signal changing unit(210), a mixer unit(220), and a calculating unit(230). The mixer unit changes an I signal and a Q signal inputted from an I/Q signal input unit according to an oscillation signal generated from an oscillator. The calculating unit adds up or deducts the I and Q signals inputted the mixer unit in order to generate an output signal. The I/Q signal changing unit adjusts a path and a symbol of the I and Q signals inputted from the calculating unit or the mixer unit according to an I/Q control signal. [Reference numerals] (10) I/Q signal input unit; (211) First I/Q signal changing part; (212) Second I/Q signal changing part; (231) First calculator; (232) Second calculator; (240) Oscillator; (250) Oscillation signal changing unit; (30) I/Q signal processing unit
Abstract translation: 目的：提供可编程解调混频器，通过降低收发器的工艺带宽，功耗和芯片尺寸来提高收发器的性能。 构成：可编程解调混频器（20）包括I / Q信号改变单元（210），混频器单元（220）和计算单元（230）。 混频器单元根据从振荡器产生的振荡信号改变从I / Q信号输入单元输入的I信号和Q信号。 计算单元相加或减去输入混频器单元的I和Q信号，以产生输出信号。 I / Q信号改变单元根据I / Q控制信号调整从计算单元或混频器单元输入的I和Q信号的路径和符号。 （附图标记）（10）I / Q信号输入单元; （211）第一I / Q信号变换部; （212）第二I / Q信号变换部分; （231）第一计算器; （232）第二计算器; （240）振荡器; （250）振荡信号改变单元; （30）I / Q信号处理单元
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公开(公告)号：KR1020120072217A
公开(公告)日：2012-07-03
申请号：KR1020100134051
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H01P1/36
Abstract: PURPOSE: A programmable active isolator for cancelation of a leakage is provided to improve the linearity of a whole system by eliminating a leakage of RF signals without using frequency conversion. CONSTITUTION: A main isolating unit(110) is arranged in a main route. A leakage removal unit(120) including a voltage reducer(121) and a phase shifter(122) is arranged in a branch route branched off the main route and removes leaked signals. In the leakage removal unit, the voltage reducer and the phase shifter are integrated into a single chip.
Abstract translation: 目的：提供用于消除泄漏的可编程有源隔离器，通过消除RF信号的泄漏而不使用频率转换来提高整个系统的线性度。 构成：主隔离单元（110）布置在主路线上。 在从主路径分支的分支路径中设置包括减压器（121）和移相器（122）的泄漏去除单元（120），并且去除泄漏的信号。 在泄漏去除单元中，降压器和移相器集成到单个芯片中。
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公开(公告)号：KR1020110070675A
公开(公告)日：2011-06-24
申请号：KR1020100027986
申请日：2010-03-29
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A digital RF converter, and a digital RF modulator and a transmitter including the same are provided to effectively increase the dynamic area and SNR of the transmitter without increasing the number of digital RF converting cells. CONSTITUTION: A DSMB(Delta-sigma modulated bits) sub block(331) creates the current of a size corresponding to the lowest n bit of input signals at a first sampling rate. An LSB(Least-Significant Bit) sub block(332) creates the current of a size corresponding to a middle k bit of the input signal at a second sampling rate lower than the first sampling rate. An MSB(Most-Significant Bit) sub block(333) creates the current of a size corresponding to the highest m bit of the input signal at the second sampling rate.
Abstract translation: 目的：提供数字RF转换器，数字RF调制器和包括该数字RF调制器的发射器，以有效增加发射机的动态面积和SNR，而不增加数字RF转换单元的数量。 构成：DSMB（Δ-Σ调制比特）子块（331）以第一采样率产生与最低n位输入信号相对应的大小的电流。 LSB（最低有效位）子块（332）以低于第一采样率的第二采样率产生与输入信号的中间k位相对应的大小的电流。 MSB（最高有效位）子块（333）以第二采样率产生与输入信号的最高m位相对应的大小的电流。
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公开(公告)号：KR1020040056692A
公开(公告)日：2004-07-01
申请号：KR1020020083234
申请日：2002-12-24
Applicant: 한국전자통신연구원
IPC: H03G3/00
Abstract: PURPOSE: A variable gain amplifier is provided to obtain characteristics such as high linearity and low noise by varying continuously gains according to input control voltages. CONSTITUTION: A variable gain amplifier includes a control signal generator, a variable resistor, and a differential amplifier. The control signal generator(210) is used for converting an external control voltage, dividing the external control voltage into a plurality of levels, and outputting the divided external control voltages as plural internal control signals. The variable resistor is used for providing variable resistance values according to the internal control signals. The differential amplifier(230) includes a parallel coupling differential amplifier having different W/L to amplify a differential element between an inverting signal and a non-inverting signal.
Abstract translation: 目的：提供可变增益放大器，以通过根据输入控制电压连续增益来获得诸如高线性度和低噪声的特性。 构成：可变增益放大器包括控制信号发生器，可变电阻器和差分放大器。 控制信号发生器（210）用于转换外部控制电压，将外部控制电压分成多个电平，并将分压的外部控制电压作为多个内部控制信号输出。 可变电阻用于根据内部控制信号提供可变电阻值。 差分放大器（230）包括具有不同W / L的并联耦合差分放大器，以放大反相信号和非反相信号之间的差分元件。
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Patent Agency Ranking
公开(公告)号：KR100422394B1
公开(公告)日：2004-03-11
申请号：KR1020010083458
申请日：2001-12-22
Applicant: 한국전자통신연구원
IPC: H03L7/00
Abstract: PURPOSE: An even order term harmonic frequency multiplier is provided to expand the bandwidth of a frequency and reduce harmonic components of the remaining order terms except for even order terms by using a frequency multiplier. CONSTITUTION: A harmonic frequency multiplier of an even order term includes a phase integrator(21), a memory(22), a digital/analog converter(23), a low pass filter(24), and a frequency multiplier(25). The phase integrator generates a period signal corresponding to a frequency control signal received from the outside. The memory is used for storing a trigonometric function value corresponding to the output of the phase integrator. The digital/analog converter is used for converting the trigonometric function value to an analog signal. The low pass filter is used for removing components of harmonics from a radio frequency of the digital/analog converter. The frequency multiplier is used for attenuating the basic components of harmonics from an output signal of the low pass filter in order to generate the higher frequency than the frequency of the output of the low pass filter.
Abstract translation: 目的：提供一个偶次序谐波倍频器，用于扩大频率的带宽，并通过使用倍频器减少剩余次序项的谐波分量，除了偶次项。 构成：偶次项的谐波倍频器包括相位积分器（21），存储器（22），数/模转换器（23），低通滤波器（24）和倍频器（25）。 相位积分器产生对应于从外部接收的频率控制信号的周期信号。 存储器用于存储对应于相位积分器输出的三角函数值。 数字/模拟转换器用于将三角函数值转换为模拟信号。 低通滤波器用于从数字/模拟转换器的射频中去除谐波成分。 倍频器用于衰减来自低通滤波器的输出信号的谐波的基本分量，以产生比低通滤波器的输出的频率更高的频率。
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27.发明公开스퓨리어스 및 수신 밴드 잡음을 감소시키는 포락선 모듈레이터 및 이를 구비한 포락선 추적 전력 증폭장치 审中-实审用于减少噪声噪声和接收带噪声的信号跟踪调制器和带有跟踪调制器的功率放大器
公开(公告)号：KR1020160096288A
公开(公告)日：2016-08-16
申请号：KR1020150017630
申请日：2015-02-04
Applicant: 한국전자통신연구원
CPC classification number: H03F1/0227 , H03F3/24 , H03F2200/102
Abstract: 무선통신단말기및/또는무선통신시스템에장착되는고효율, 고선형성의전력증폭장치의전원공급부에선형및 스위칭신호를인가하는포락선모듈레이터및 이를구비한포락선추적전력증폭장치가개시된다. 포락선추적전력증폭장치는포락선입력신호를증폭하여증폭된포락선신호를출력하는넓은대역폭을가지는포락선모듈레이터와, 상기증폭된포락선신호에따라 RF 신호를증폭하여증폭된 RF 신호를출력하는전력증폭기, 그리고상기포락선모듈레이터의출력단에병렬로연결된커패시터를포함할수 있다.
Abstract translation: 公开了一种将无线通信终端和/或无线通信系统中安装的线性和切换信号施加到功率放大器的电源部件，并且具有高效率和高线性度的包络调制器，以及包括其的包络跟踪功率放大器 。 包络跟踪功率放大器可以包括：包络调制器，其具有宽带宽以放大包络输入信号并输出放大的包络信号; 功率放大器，根据放大的包络信号放大RF信号，然后输出放大的RF信号; 以及并联连接到包络调制器的输出级的电容器。 本发明通过减少功率放大器的输出的杂散噪声和接收机频带噪声来实现具有高效率和高线性度的功率放大器来促进低噪声无线通信。
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公开(公告)号：KR1020120072216A
公开(公告)日：2012-07-03
申请号：KR1020100134050
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H03M1/66
CPC classification number: H03M1/0653 , H03M1/685 , H03M1/747
Abstract: PURPOSE: A digital analog converter and a method for correcting a current source of the digital analog converter are provide to reduce an area of circuit by digitizing the most of a circuit for correcting a digital analog converter. CONSTITUTION: A current comparator(120) compares currents from two current sources(110) by receiving addresses of the two current sources from a comparison signal generator(160). A group address, which is arranged according to the size of the current from the current source bound in a group, is saved in a group array register(140). The address, which is arranged according to the size of the current from the current source, is saved in the unit array register. An non-group register(170) stores a grouped address by receiving the address from the group array register and the unit array register. An RAM data generator(180) generates a mapping table stored in mapping memory(190). A comparison signal generator generates a control signal. A array controller(130) arrays the address of the current source.
Abstract translation: 目的：数字模拟转换器和用于校正数字模拟转换器的电流源的方法通过数字化用于校正数字模拟转换器的电路的大部分来减小电路的面积。 构成：电流比较器（120）通过从比较信号发生器（160）接收两个电流源的地址来比较来自两个电流源（110）的电流。 组地址，其被按照组中的当前源的当前源的大小进行排列，被保存在组数组寄存器（140）中。 根据当前源的电流大小排列的地址保存在单元阵列寄存器中。 非组寄存器（170）通过从组阵列寄存器和单元阵列寄存器接收地址来存储分组地址。 RAM数据生成器（180）生成存储在映射存储器（190）中的映射表。 比较信号发生器产生控制信号。 阵列控制器（130）对当前源的地址进行排列。
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公开(公告)号：KR1020110040656A
公开(公告)日：2011-04-20
申请号：KR1020100081571
申请日：2010-08-23
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A digital RF converter and an RF converting method thereof are provided to prevent unnecessary power consumption by using only the current source corresponding to total current quantity at an RF path. CONSTITUTION: A DRFC(Digital to RF Converter)(21c) comprises a digital preprocessor(270) and a plurality of blocking switches(2800 to 280N). The digital preprocessor receives the output of a digital delay device(2620 to 262N+1). The digital preprocessor generates a control signal for operating a current switch(2640 to 264N) and a blocking switch. The blocking switch is electrically connected in response to the control signal.
Abstract translation: 目的：提供数字RF转换器及其RF转换方法，以通过仅使用与RF路径上的总电流量相对应的电流源来防止不必要的功率消耗。 构成：DRFC（数字到RF转换器）（21c）包括数字预处理器（270）和多个阻塞开关（2800至280N）。 数字预处理器接收数字延迟器（2620〜262N + 1）的输出。 数字预处理器产生用于操作电流开关（2640至264N）和阻塞开关的控制信号。 阻塞开关响应于控制信号被电连接。
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公开(公告)号：KR100723838B1
公开(公告)日：2007-05-31
申请号：KR1020050078825
申请日：2005-08-26
Applicant: 한국전자통신연구원
IPC: H03L7/085
Abstract: 본 발명은 주파수 합성 장치를 개시한다.
본 발명에 의하면, 주파수가 분주된 신호와 기준 신호의 주파수의 차이에 따라 가변되는 전압에 따른 주파수를 출력하며, 출력된 주파수를 피드백하여 위상 고정 루프 제어하는 PLL 루프, 주파수 분주된 신호와 기준 신호의 주파수 차이에 대응하는 신호의 전압에 따른 주파수를 출력하며, 출력된 신호를 피드백하여 적응적으로 주파수를 교정하는 AFC 루프 및 출력되는 신호의 주파수를 소정의 비율에 따라 분주한 주파수가 기준 신호의 주파수에 소정의 범위 내에 접근하기 전에는 AFC 루프만 동작하게 하고, 분주한 주파수가 기준 주파수에 소정의 범위 내에 접근하면 AFC 루프의 동작을 중지시키고 PLL 루프만 동작하도록 제어하는 락 검출부를 포함하여, 전하펌프의 출력 DC 전위를 전하펌프의 전류원의 DC 전류의 오차가 최소화된 영역에서 동작하도록 하여 종래에 비해 주파수 순도 특성을 개선하는 효과가 있으며, 또한 PLL 루프의 위상 마진을 확보하기 위해서는 전압제어 발진기의 이득이 일정해야 되는데, 본 발명을 이용하여 전압제어발진기의 이득이 비교적 일정해지는 효과를 제공한다.
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