公开(公告)号：DE60129605D1

公开(公告)日：2007-09-06

申请号：DE60129605

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L21/00 ,  H01L27/10 ,  H01L21/8242

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

公开(公告)号：DE10334946B4

公开(公告)日：2006-03-09

申请号：DE10334946

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

公开(公告)号：DE10307822B4

公开(公告)日：2005-08-18

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：GB2497849B

公开(公告)日：2016-02-03

申请号：GB201222136

申请日：2012-12-10

Applicant: IBM

Inventor： YAMASHITA TENKO ,  DIVAKARUNI RAMACHANDRA ,  BU HUIMING ,  SHANG HUILING ,  CHUNG-HSUN LIN ,  ANDO TAKASHI ,  DORIS BRUCE B

IPC: H01L29/66 ,  H01L29/78

Abstract: A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.

公开(公告)号：DE102012223655B4

公开(公告)日：2015-02-26

申请号：DE102012223655

申请日：2012-12-18

Applicant: IBM

Inventor： ANDO TAKASHI ,  BU HUIMING ,  DORIS BRUCE B ,  LIN CHUNG-HSUN ,  SHANG HUILING ,  YAMASHITA TENKO ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/268

Abstract: Verfahren zur Herstellung eines Feldeffekttransistors, aufweisend: Bilden einer Platzhalter-Gate-Struktur, die aus einem Stopfen besteht, auf einer Fläche eines Halbleiters; Bilden eines ersten Abstandhalters, welcher den Stopfen umgibt, wobei der erste Abstandhalter ein Opfer-Abstandhalter ist; und Durchführen einer abgewinkelten Ionenimplantation, um in Nachbarschaft zu einer äußeren Seitenwand des ersten Abstandhalters eine Dotierstoffspezies in die Fläche des Halbleiters zu implantieren, um eine Source-Erweiterungszone und eine Drain-Erweiterungszone zu bilden, wobei sich die implantierte Dotierstoffspezies in einem Ausmaß unter der äußeren Seitenwand des ersten Abstandhalters erstreckt, welches eine Funktion des Winkels der Ionenimplantation ist; und Durchführen eines Laser-Temperns, um die Implantation der Source-Erweiterung und der Drain-Erweiterung zu aktivieren.

公开(公告)号：DE102012223655A1

公开(公告)日：2013-06-27

申请号：DE102012223655

申请日：2012-12-18

Applicant: IBM

Inventor： ANDO TAKASHI ,  BU HUIMING ,  DORIS BRUCE B ,  LIN CHUNG-HSUN ,  SHANG HUILING ,  YAMASHITA TENKO ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/336 ,  H01L29/78

Abstract: Ein Verfahren weist das Bilden einer Platzhalter-Gate-Struktur, welche aus einem Stopfen besteht, auf einer Fläche eines Halbleiters; das Bilden eines ersten Abstandhalters, welcher den Stopfen umgibt, wobei der erste Abstandhalter ein Opfer-Abstandhalter ist; und das Durchführen einer abgewinkelten Ionenimplantation auf, um in Nachbarschaft zu einer äußeren Seitenwand des ersten Abstandhalters eine Dotierstoffspezies in die Fläche des Halbleiters zu implantieren, um eine Source-Erweiterungszone und eine Drain-Erweiterungszone zu bilden, wobei sich die implantierte Dotierstoffspezies in einem Ausmaß unter der äußeren Seitenwand des ersten Abstandhalters erstreckt, welches eine Funktion des Winkels der Ionenimplantation ist. Das Verfahren weist ferner das Durchführen eines Laser-Temperns auf, um die Implantation der Source-Erweiterung und der Drain-Erweiterung zu aktivieren. Das Verfahren weist ferner das Bilden eines zweiten Abstandhalters, welcher den ersten Abstandhalter umgibt, das Entfernen des ersten Abstandhalters und des Stopfens, um eine Öffnung zu bilden, und das Abscheiden eines Gate-Stapels in der Öffnung auf.

公开(公告)号：DE10307822A1

公开(公告)日：2003-11-06

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：DE60133214T2

公开(公告)日：2009-04-23

申请号：DE60133214

申请日：2001-11-13

Applicant: IBM ,  QIMONDA AG

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

公开(公告)号：DE10361272A1

公开(公告)日：2004-08-05

申请号：DE10361272

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242

Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.