公开(公告)号：DE2425382A1

公开(公告)日：1975-01-02

申请号：DE2425382

申请日：1974-05-25

Applicant: IBM

Inventor： JOHNSON WILLIAM STANFORD ,  KU SAN-MEI

IPC: H01L21/283 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/322 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/00 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

Abstract: A method for manufacturing insulated gate field effect transistor devices utilizing ion implantation for elimination and suppression of mobile ion contamination is described and comprises bombarding and implanting hydrogen or helium into the dielectric insulating layer of an insulated gate field effect transistor at relatively low ion energy, followed by a comparatively low temperature anneal.

公开(公告)号：DE69023951T2

公开(公告)日：1996-06-20

申请号：DE69023951

申请日：1990-03-27

Applicant: IBM

Inventor： KU SAN-MEI ,  PERRY KATLEEN ALICE

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/302 ,  H01L21/331 ,  H01L21/768 ,  H01L29/732 ,  H01L21/311

Abstract: A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate (26) having at least two features e.g. a polysilicon land (36), another polysilicon land (48), and substrate (26),thereon whereat it is desired to make electrical connections; forming a layer (54) of etch stop material having a first etch characteristic over each of the features; forming a layer (56) of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias (58, 66, 60) through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections (76, 74, 78).

公开(公告)号：CA2011235A1

公开(公告)日：1990-11-15

申请号：CA2011235

申请日：1990-03-01

Applicant: IBM

Inventor： KU SAN-MEI ,  PERRY KATHLEEN A

IPC: H01L29/73 ,  H01L21/285 ,  H01L21/302 ,  H01L21/331 ,  H01L21/768 ,  H01L29/732

Abstract: A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate (26) having at least two features e.g. a polysilicon land (36), another polysilicon land (48), and substrate (26),thereon whereat it is desired to make electrical connections; forming a layer (54) of etch stop material having a first etch characteristic over each of the features; forming a layer (56) of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias (58, 66, 60) through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections (76, 74, 78).

公开(公告)号：DE3380614D1

公开(公告)日：1989-10-26

申请号：DE3380614

申请日：1983-03-15

Applicant: IBM

Inventor： GLANG REINHARD ,  KU SAN-MEI ,  SCHMITT ALFRED

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/01 ,  H01L27/04 ,  H01L21/31

Abstract: A method for making polycrystalline silicon film resistors is described which includes deposition of a polycrystalline silicon layer (14, 34) of very fine grain size upon an insulator surface (12, 28), followed by ion implantation of boron equal to or slightly in excess of the solubility limit of the polycrystalline silicon. This ion implantation is normally done using a screen silicon dioxide surface layer. The structure may be annealed at temperatures of between 800°C to 1100°C for 15 to 180 minutes to control the grain size of the polycrystalline silicon layer, homogenize the distribution of the boron ions throughout the entire film thickness and to raise the concentration of the boron in the silicon grains to the solid solubility limit. The suitable electrical contacts (52, 54) are now made to the polycrystalline silicon layer to form the resistor.

公开(公告)号：CA1032658A

公开(公告)日：1978-06-06

申请号：CA201600

申请日：1974-06-04

Applicant: IBM

Inventor： KU SAN-MEI ,  PILLUS CHARLES A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/322 ,  H01L21/336 ,  H01L23/522 ,  H01L23/532

公开(公告)号：FR2357067A1

公开(公告)日：1978-01-27

申请号：FR7716061

申请日：1977-05-18

Applicant: IBM

Inventor： DEINES JOHN L ,  KU SAN-MEI ,  POPONIAK MICHAEL R ,  TSANG PAUL J

IPC: C30B25/02 ,  C30B29/36 ,  H01L21/04 ,  H01L21/205 ,  H01L21/762 ,  H01L29/267 ,  H01L21/314

Abstract: A method for forming monocrystalline silicon carbide on a silicon substrate by converting a portion of the monocrystalline silicon substrate into a porous silicon substance by anodic treatment carried out in an aqueous solution of hydrofluoric acid, heating the resultant substrate to a temperature in the range of 1050 DEG C to 1250 DEG C in an atmosphere that includes a hydrocarbon gas for a time sufficient to react the porous silicon and the gas, thereby forming a layer of monocrystalline silicon carbide on the silicon substrate.

公开(公告)号：FR2305853A1

公开(公告)日：1976-10-22

申请号：FR7603001

申请日：1976-01-29

Applicant: IBM

Inventor： KU SAN-MEI ,  PILLUS CHARLES A ,  POPONIAK MICHAEL R ,  SCHWENKER ROBERT O

IPC: C30B31/22 ,  H01L21/22 ,  H01L21/265 ,  H01L21/761

Abstract: In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation regions. In one embodiment, an epitaxial layer of one conductivity-type is formed on a substrate of opposite conductivity-type, after which dopant ions of the opposite conductivity-type are introduced into the epitaxial surface areas which are to provide the base and isolation regions, and in addition, the isolation regions are bombarded with non-dopant ions having a maximum atomic number of two, e.g., hydrogen or helium ion while the base regions are appropriately masked and remain umbombarded, said bombardment is carried out at temperatures below 300 DEG C, preferably room temperature. The bombardment is preferably carried out so that the non-dopant ions are implanted primarily in regions below the isolation regions. Next, the wafer is heated at a temperature at a range of from 600 DEG - 900 DEG C which is substantially below normal drive-in diffusion temperatures for unbombarded doped regions. The heating to be maintained for a period sufficient to drive-in diffuse the bombarded isolation regions through the epitaxial layer into contact with the substrate but is insufficient to drive-in the unbombarded base regions to such a depth.

公开(公告)号：FR2292332A1

公开(公告)日：1976-06-18

申请号：FR7530734

申请日：1975-10-01

Applicant: IBM

Inventor： JOHNSON CLAUDE JR ,  KU SAN-MEI ,  LILLJA HAROLD V ,  PAN EDWARD SHIH-TO

IPC: H01L21/266 ,  G03F7/40 ,  H01L21/00 ,  H01L21/56 ,  H01L21/265 ,  G03F1/02

Abstract: An improvement in the method of ion implantation into a semiconductor substrate through a photoresist mask wherein the photoresist mask is subjected to an RF gas plasma oxidation prior to the ion implantation step for a period sufficient to reduce the thickness of the photoresist layer. The ion implantation is then carried out through the treated photoresist mask.

公开(公告)号：DE2534801A1

公开(公告)日：1976-05-26

申请号：DE2534801

申请日：1975-08-05

Applicant: IBM

Inventor： JOHNSON JUN CLAUDE ,  KU SAN-MEI ,  LILLJA HAROLD VINELL ,  PAN EDWARD SHIH-TO

IPC: H01L21/266 ,  G03F7/40 ,  H01L21/00 ,  H01L21/56 ,  H01L21/265

Abstract: An improvement in the method of ion implantation into a semiconductor substrate through a photoresist mask wherein the photoresist mask is subjected to an RF gas plasma oxidation prior to the ion implantation step for a period sufficient to reduce the thickness of the photoresist layer. The ion implantation is then carried out through the treated photoresist mask.