公开(公告)号：GB2493238B

公开(公告)日：2014-04-16

申请号：GB201208558

申请日：2011-04-26

Applicant: IBM

Inventor： CHEN KUAN-NENG ,  LIN YU-MING ,  AVOURIS PHAEDON ,  FARMER DAMON BROOKS

IPC: H01L21/822 ,  B82Y10/00 ,  H01L27/06 ,  H01L27/12 ,  H01L29/16 ,  H01L29/786

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

公开(公告)号：GB2487308B

公开(公告)日：2014-03-05

申请号：GB201201184

申请日：2010-08-31

Applicant: IBM

Inventor： LIN YU-MING ,  JENKINS KEITH AELWYN ,  GARCIA ALBERTO VALDES

IPC: H01L29/786

公开(公告)号：GB2499311A

公开(公告)日：2013-08-14

申请号：GB201300509

申请日：2013-01-11

Applicant: IBM

Inventor： DIMITRAKOPOULOS CHRISTOS ,  GRILL ALFRED ,  NEUMAYER DEBORAH ANN ,  PFEIFFER DIRK ,  ZHU WENJUAN ,  FARMER DAMON BROOKS ,  LIN YU-MING

IPC: H01L29/786 ,  B82Y40/00 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

Abstract: A silicon nitride layer 16 is provided on an uppermost surface of a graphene layer 14 and then a hafnium dioxide layer 18 is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer. The graphene layer can be epitaxially grown on a substrate which may be silicon carbide. The silicon nitride layer may be a tensile silicon nitride layer. A portion of the graphene layer may serve as a channel layer for a FET. The graphene layer may be in contact with source and drain regions of an FET 56, 58. A gate conductor 54 may be located on the hafnium oxide layer. The dielectric bilayer may cover the sides and the top of the source drain regions.

公开(公告)号：GB2497248A

公开(公告)日：2013-06-05

申请号：GB201305445

申请日：2011-07-20

Applicant: IBM

Inventor： AVOURIS PHAEDON ,  FARMER DAMON BROOKS ,  LIN YU-MING ,  ZHU YU

IPC: H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.