公开(公告)号：JPH11163146A

公开(公告)日：1999-06-18

申请号：JP27611398

申请日：1998-09-29

Applicant: SIEMENS AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  DINKEL BETTINA

IPC: H01L21/82 ,  H01L23/31 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To conform a small TV window to a precursory fuse designing specification, which covers only a small space. SOLUTION: After the formation of a sensing soft passivation film 150, an etching stopper film 130 is used so as to set up a terminal through the intermediary of an aperture 132 to access a device feature part. As a result of etching film, the size of the terminal set up through the intermediary of the aperture 132 through an etching film is decided by decoupling with the decomposition activity of the existing photosensing soft passivation film 150.

公开(公告)号：JPH11154739A

公开(公告)日：1999-06-08

申请号：JP25842598

申请日：1998-09-11

Applicant: SIEMENS AG ,  IBM

Inventor： WEIGAND PETER ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH C ,  LACHTRUPP DAVID ,  GILMOUR RICHARD ALFRED ,  PALAGONIA ANTHONY MICHAEL

IPC: H01L21/82 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To minimize damage to a substrate being subjected to fuse operation and to reduce the fuse pitch, by arranging a screening part where a laser fuse link is set by laser beams so that the damage of laser induction from laser beams is minimized at a region below the screening part. SOLUTION: A dynamic access memory integrated circuit has a plurality of screening parts 402, 404, 406, and 408 located on the lower side of laser fuse links 202, 204, 206, and 208. The screening parts are constituted so that a first regions located on the lower side of the screening parts can be essentially minimized when the first laser fuse links are set by laser beams. The screening part is formed by a material for reflecting nearly entire laser energy applied the screening part. A reflection material such as tungsten, molybdenum, platinum, chromium, titanium, and their alloys operates favorably.

公开(公告)号：DE60307793T2

公开(公告)日：2007-08-23

申请号：DE60307793

申请日：2003-02-27

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： IYER S SUNDAR K ,  IYER SUBRAMANIAN S ,  KOTHANDARAMAN CHANDRASEKHARAN ,  NARAYAN CHANDRASEKHAR

IPC: H01L23/525

Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.

公开(公告)号：DE60034611D1

公开(公告)日：2007-06-14

申请号：DE60034611

申请日：2000-02-04

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： WEBER STEFAN J ,  IGGULDEN ROY ,  NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL CHRISTOPH ,  HOINKIS MARK ,  VAN DEN BERG ROBERT

IPC: H01H85/00 ,  H01H69/02 ,  H01L23/525 ,  H01L21/82

Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.

公开(公告)号：DE69633998T2

公开(公告)日：2005-12-22

申请号：DE69633998

申请日：1996-09-04

Applicant: IBM

Inventor： CIPOLLA THOMAS M ,  COLGAN EVAN ,  MELCHER ROBERT L ,  MOK LAWRENCE S ,  NARAYAN CHANDRASEKHAR ,  SHI LEATHEN ,  YANG KEI-HSIUNG

IPC: G02F1/13 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/136 ,  G09F9/00 ,  H04N5/74 ,  G02F1/1335 ,  H04N9/31

Abstract: A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal. During mounting, an aligning fixture is used to ensure proper orientation of the element relative to the related optical elements. Once the element is positioned, a heat sink is coupled to the rear surface of the substrate holder to dissipate heat.

公开(公告)号：GB2355327B

公开(公告)日：2004-02-18

申请号：GB0017095

申请日：2000-07-13

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  STORASKA DANIEL ,  NARAYAN CHANDRASEKHAR ,  TONTI WILLIAM ,  BERTIN CLAUDE ,  VAN HEEL NICK

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/112

Abstract: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.

公开(公告)号：DE60011190D1

公开(公告)日：2004-07-08

申请号：DE60011190

申请日：2000-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

公开(公告)号：AU2002352993A1

公开(公告)日：2003-07-09

申请号：AU2002352993

申请日：2002-11-26

Applicant: IBM

Inventor： YU ROY ,  PRASAD CHANDRIKA ,  NARAYAN CHANDRASEKHAR ,  POGGE BERNHARD H

IPC: H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/8234

Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

公开(公告)号：SG35475A1

公开(公告)日：1997-02-01

申请号：SG1996000139

申请日：1996-01-10

Applicant: IBM

Inventor： NARAYAN CHANDRASEKHAR ,  SHAW JANE M

IPC: H05K1/03

公开(公告)号：MX9600738A

公开(公告)日：1997-01-31

申请号：MX9600738

申请日：1996-02-26

Applicant: IBM

Inventor： NARAYAN CHANDRASEKHAR ,  SHAW JANE M

IPC: H05K3/46 ,  H05K1/00 ,  H05K3/00 ,  H05K07/02

Abstract: La presente invencion proporciona un modulo de cableado que contiene una pluralidad de capas de polímero laminado, que contiene un grupo de circuitos electronicos definido, que puede termoformarse en formas tridimensionales deseadas sin dañar el cableado interno en la region de tension de termoformado. Más particularmente, la invencion proporciona un modulo de cableado tridimensional termoformado que se prepara al termoformar un laminado que comprende una pluralidad de capas aislantes de polímero termoformables, laminadas que contienen circuitos de cableado conductores cuando menos en una superficie de las capas, las capas están ensambladas para formar trayectorias de interconexion conductoras dentro del modulo, el modulo además está caracterizado porque los circuitos de cableado conductores están presentes solo en capas de baja tension internas de laminado en la region de doblez de termoformado presente en el modulo.