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公开(公告)号：CA2273719C
公开(公告)日：2004-03-30
申请号：CA2273719
申请日：1999-06-04
Applicant: IBM
Inventor： FUHS RONALD E , BEUKEMA BRUCE L , THURBER STEVEN MARK , NEAL DANNY M , KELLEY RICHARD A
Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 1 00 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking da ta on only one clock edge, or by clocking data on both a rising edge and a falling edge of a cloc k signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions o r alias split transactions to delayed transactions. Backward compatibility may also be provided for option al features such as hot-pluggability.
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公开(公告)号：CA2273719A1
公开(公告)日：2000-01-15
申请号：CA2273719
申请日：1999-06-04
Applicant: IBM
Inventor： BEUKEMA BRUCE L , THURBER STEVEN MARK , NEAL DANNY M , FUHS RONALD E , KELLEY RICHARD A
Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
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公开(公告)号：MY124400A
公开(公告)日：2006-06-30
申请号：MYPI9905176
申请日：1999-11-26
Applicant: IBM
Inventor： NEAL DANNY MARVIN , THURBER STEVEN MARK
Abstract: AN APPARATUS AND METHOD FOR MEDIATING A SEQUENCE OF TRANSACTIOS ACROSS A FABRIC (120) IN A DATA PROCESSING SYSTEM (100) ARE IMPLEMENTED. A FABRIC BRIDGE (122) ORDERS A PRECEDING TRANSACTION AND A SUBSEQUENT TRANSACTION ACCORDING TO A PREDETERMINED PROTOCOL. USING THE PROTOCOL A DETERMINATION IS MADE WHETHER THE SUBSEQUENT TRANSACTION MAY BE ALLOWED TO BYPASS THE PREVIOUS TRANSACTION, MUST BE ALLOWED TO BYPASS THE PREVIOUS TRANSACTION, OR MUST NOT BE ALLOWED TO BYPASS THE PRECEDING TRANSACTION. TRANSACTIONS INCLUDE LOAD/STORE (L/S) TO SYSTEM MEMORY (108), AND DIRECT MEMORY ACCESS (DMA) TO SYSTEM MEMORY TRANSACTIONS. (FIG.1)
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公开(公告)号：BR0003217A
公开(公告)日：2001-03-13
申请号：BR0003217
申请日：2000-07-31
Applicant: IBM
Inventor： KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVEN MARK
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40 , G06F13/366
Abstract: A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.
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公开(公告)号：DE69419680T2
公开(公告)日：2000-03-02
申请号：DE69419680
申请日：1994-09-15
Applicant: IBM
Inventor： ARNDT RICHARD LOUIS , NICHOLSON JAMES OTTO , SILHA EDWARD JOHN , THURBER STEVEN MARK , YOUNGS AMY MAY
Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.
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Patent Agency Ranking
公开(公告)号：ID21264A
公开(公告)日：1999-05-12
申请号：ID980644
申请日：1998-04-30
Applicant: IBM
Inventor： CLOUSER PAUL L , JOHNS CHARLES RAY , KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVEN MARK
IPC: G06F13/00 , G06F13/368 , G06F13/38
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公开(公告)号：MY124338A
公开(公告)日：2006-06-30
申请号：MYPI9905175
申请日：1999-11-26
Applicant: IBM
Inventor： NEAL DANNY MARVIN , THURBER STEVEN MARK
Abstract: AN APPARATUS AND METHOD FOR MEDIATING A SEQUENCE OF TRANSACTIONS ACROSS A FABRIC IN A DATA PROCESSING SYSTEM ARE IMPLEMENTED. A FABRIC BRIDGE ORDERS A PRECEDING TRANSACTION AND A SUBSEQUENT TRANSACTION ACCORDING TO A PREDETERMINED PROTOCOL. USING THE PROTOCOL A DETERMINATION IS MADE WHETHER THE SUBSEQUENT TRANSACTION MAY BE ALLOWED TO BYPASS THE PREVIOUS TRANSACTION, MUST BE ALLOWED TO BYPASS THE PREVIOUS TRANSACTION, OR MUST NOT BE ALLOWED TO BYPASS THE PRECEDING TRANSACTION. TRANSACTIONS INCLUDE LOAD/STORE (L/S) SYSTEM MEMORY AND L/S TO INPUT/ OUTPUT (I/O) DEVICE, AND DIRECT MEMORY ACCESS (DMA) TO SYSTEM MEMORY AND DMA PEER-TO-PEER TRANSACTIONS.
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公开(公告)号：HK1028831A1
公开(公告)日：2001-03-02
申请号：HK00108160
申请日：2000-12-18
Applicant: IBM
Inventor： NEAL DANNY MARVIN , THURBER STEVEN MARK
Abstract: An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) system memory and L/S to input/output (I/O) device, and direct memory access (DMA) to system memory and DMA peer-to-peer transactions.
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公开(公告)号：IE990422A1
公开(公告)日：2000-03-22
申请号：IE990422
申请日：1999-05-25
Applicant: IBM
Inventor： NEAL DANNY MARVIN , THURBER STEVEN MARK , BEUKEMA BRUCE LEROY , FUHS RONALD EDWARD , KELLEY RICHARD ALLEN
IPC: G06F13/40 , G06F13/368
Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
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公开(公告)号：CA2236060A1
公开(公告)日：1998-12-11
申请号：CA2236060
申请日：1998-04-28
Applicant: IBM
Inventor： NEAL DANNY MARVIN , THURBER STEVEN MARK , CLOUSER PAUL L , JOHNS CHARLES RAY , KELLEY RICHARD ALLEN
IPC: G06F13/00 , G06F13/368 , G06F13/38
Abstract: A peripheral component interconnect (PCI) bus is adapted for differential signal ling. Two signal lines are providing for each bus signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. En hanced PCI compliant devices include drivers and receivers capable of differential sign alling. The resulting bus architecture supports clocking data on both edges as well as sourc e synchronous clocking. The enhanced PCI bus architecture also supports data block ing, pacing, split transactions, and synchronization commands.
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