公开(公告)号：AT457081T

公开(公告)日：2010-02-15

申请号：AT01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN ,  HO HERBERT ,  HOINKIS MARK ,  LEE HYUN ,  WANG YUN-YU ,  WONG KWONG

IPC: C23C16/34 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/532

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：DE102004017411A1

公开(公告)日：2005-03-10

申请号：DE102004017411

申请日：2004-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  UNITED MICROELECTRONICS CO

Inventor： COWLEY ANDY ,  FANG SUNFEI ,  WANG YUN-YU ,  CLEVENGER LARRY ,  SIMON ANDREW H ,  GRECO STEPHEN ,  CHANDA KAUSHIK ,  SPOONER TERRY ,  YANG CHIH-CHAO

IPC: H01L21/768 ,  H01L21/285

公开(公告)号：AU2003298347A1

公开(公告)日：2004-06-30

申请号：AU2003298347

申请日：2003-12-08

Applicant: IBM

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  TULIPE DOUGLAS JR LA ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：AU2002241651A1

公开(公告)日：2002-07-24

申请号：AU2002241651

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WONG KWONG HON ,  LEE HYUN KOO ,  WANG YUN-YU ,  HO HERBERT L ,  HOINKIS MARK ,  BOETTCHER STEVEN H

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.