公开(公告)号：DE50113843D1

公开(公告)日：2008-05-29

申请号：DE50113843

申请日：2001-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN ,  MANYOKI ZOLTAN

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/3185 ,  G11C29/04 ,  G11C29/24

Abstract: An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

公开(公告)号：DE50110011D1

公开(公告)日：2006-07-20

申请号：DE50110011

申请日：2001-07-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  ROEHR THOMAS DR ,  GOGL DIETMAR

IPC: G11C8/08 ,  G11C11/14 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: An electronic driver connection for a memory matrix wordlines comprises a driver source (2) having many coded outputs (IV0 - IV3, V0). Many wordline switches (N1-16, P1-8) are controllable by a control signal (SLNP;SLN1;SLN2) and switchably connect the drive source output to the word lines. Independent claims are also included for the following: (a) a memory device according to the above; and (b) a nonvolatile magnetic semiconductor memory for the above.

公开(公告)号：DE10014385B4

公开(公告)日：2005-12-15

申请号：DE10014385

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANYOKI ZOLTAN ,  ESTERL ROBERT ,  BOEHM THOMAS ,  LAMMERS STEFAN

IPC: G05F3/24 ,  H01L23/58 ,  H01L27/085 ,  H03H11/00

公开(公告)号：DE50000970D1

公开(公告)日：2003-01-30

申请号：DE50000970

申请日：2000-03-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C7/14 ,  G11C11/22

Abstract: An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

公开(公告)号：DE59902239D1

公开(公告)日：2002-09-05

申请号：DE59902239

申请日：1999-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NEUHOLD ERNST ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  BOEHM THOMAS ,  ROEHR THOMAS

IPC: G11C11/22 ,  G06F11/20 ,  G11C29/00 ,  G11C29/04

Abstract: An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

公开(公告)号：DE10045042C1

公开(公告)日：2002-05-23

申请号：DE10045042

申请日：2000-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN ,  BOEHM THOMAS

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: Single memory cell fields from memory arrays (A) and peripheral circuits (P) assigned to these are interlaced into each other so that utilizing free corner surfaces in a cross-shaped structure produces a high packing density for a module structure. Rows (1-3) in an MRAM module structure are offset to each other so that in row 2, for example, the peripheral circuits bordering on rows 1 and 3 fit in exactly to the corner surfaces of the memory cell fields in rows 1 and 3.

公开(公告)号：DE50100269D1

公开(公告)日：2003-07-03

申请号：DE50100269

申请日：2001-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DR ,  FREITAG DR ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: Single memory cell fields from memory arrays (A) and peripheral circuits (P) assigned to these are interlaced into each other so that utilizing free corner surfaces in a cross-shaped structure produces a high packing density for a module structure. Rows (1-3) in an MRAM module structure are offset to each other so that in row 2, for example, the peripheral circuits bordering on rows 1 and 3 fit in exactly to the corner surfaces of the memory cell fields in rows 1 and 3.

公开(公告)号：DE10132849A1

公开(公告)日：2003-01-23

申请号：DE10132849

申请日：2001-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAMMERS STEFAN ,  BOEHM THOMAS ,  ROEHR THOMAS

IPC: G11C8/12 ,  G11C11/16 ,  G11C11/15

Abstract: The memory elements are provided in memory areas (2) to which selection devices (5,7) are assigned. The memory areas are selectively controlled using each selection device during operating mode.

公开(公告)号：DE10002374C2

公开(公告)日：2002-10-17

申请号：DE10002374

申请日：2000-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/406

Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.

公开(公告)号：DE10061693A1

公开(公告)日：2002-06-27

申请号：DE10061693

申请日：2000-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/22

Abstract: The operating method has the plate lines (PL) associated with a group (20) of memory cells (10) combined, with the potentials of the combined plate lines for all the memory cells in the group altered simultaneously or in common at a relatively rapid variation rate, obtained by providing a relatively small plate line impedance.