公开(公告)号：DE10250156A1

公开(公告)日：2004-05-13

申请号：DE10250156

申请日：2002-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: G11C5/04 ,  G11C5/06 ,  H05K1/14 ,  G11C7/10 ,  G11C7/02

Abstract: In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.

公开(公告)号：DE10124768A1

公开(公告)日：2002-12-12

申请号：DE10124768

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  BENEDIX ALEXANDER ,  KLEHN BERND ,  KRAUSE GUNNAR

IPC: G06F9/50 ,  G06F15/16

公开(公告)号：DE10124767A1

公开(公告)日：2002-12-12

申请号：DE10124767

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  BENEDIX ALEXANDER ,  KLEHN BERND

IPC: G06F12/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/16

Abstract: A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.

公开(公告)号：DE10128238C1

公开(公告)日：2002-11-28

申请号：DE10128238

申请日：2001-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG

IPC: G06F1/26

Abstract: The combining method has at least one supply voltage potential (103a) and a mass potential (107a) provided for at least one logic-based circuit module (101) and at least one supply voltage potential (103b) and a mass potential (107b) provided for at least one storage-based circuit module (102), for obtaining respective supply voltage amplitudes (111a,111b). Both circuit modules are supplied with a signal voltage amplitude (105) between defined minimum and maximum values, provided without the supply voltage amplitudes being exceeded. An Independent claim for a circuit device for combining logic-based and storage-based circuit modules is also included.

公开(公告)号：DE10002374C2

公开(公告)日：2002-10-17

申请号：DE10002374

申请日：2000-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/406

Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.

公开(公告)号：DE19919360C2

公开(公告)日：2001-09-20

申请号：DE19919360

申请日：1999-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG

IPC: G01R31/28 ,  G11C11/22 ,  G11C11/401 ,  G11C11/406 ,  G11C14/00 ,  G11C29/34

公开(公告)号：DE19931125A1

公开(公告)日：2001-01-25

申请号：DE19931125

申请日：1999-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD ,  BRAUN GEORG

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L27/105

Abstract: The invention relates to a ferroelectric transistor which has two source/drain areas (13) and a channel area between them, in a semiconductor substrate (11), and in which a first dielectric intermediate layer (14) is situated on the surface of the channel area. Above said first dielectric intermediate layer (14) are a ferroelectric layer (15), a second dielectric intermediate layer (16) and a gate electrode (17). The second dielectric intermediate layer (16) reduces the leakage currents through the ferroelectric layer (15) to the interface between the first dielectric layer (14) and the ferroelectric layer, hereby improving the data management.

公开(公告)号：DE50015406D1

公开(公告)日：2008-11-27

申请号：DE50015406

申请日：2000-12-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS DR

IPC: G11C11/406 ,  G11C14/00 ,  G11C11/22

Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.

公开(公告)号：DE102005058438A1

公开(公告)日：2007-06-14

申请号：DE102005058438

申请日：2005-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NYGREN AARON ,  BRAUN GEORG

IPC: G11C11/4063 ,  G11C7/04

Abstract: An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.

公开(公告)号：DE102005036528A1

公开(公告)日：2007-02-01

申请号：DE102005036528

申请日：2005-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  PLAETTNER ECKEHARD ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C11/4093

Abstract: The module has a scheduling circuit connected with a connection (4) for scheduling a connection with an adjustable resistance value. A control connection receives a control command signal. A control circuit (8) is connected with the scheduling circuit (5) to adjust the resistance value based on the control command signal and to schedule the connection. A control circuit is arranged in order to select one of the scheduling resistances. Independent claims are also included for the following: (1) a memory system with a memory controller (2) a method for operating a memory module.