公开(公告)号：JP2001298165A

公开(公告)日：2001-10-26

申请号：JP2001057296

申请日：2001-03-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACHHOFER HARALD ,  HARTNER WALTER ,  SCHINDLER GUENTHER DR ,  HANEDER THOMAS PETER ,  HONLEIN WOLFGANG

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To facilitate the production of a storage capacitor. SOLUTION: The crystallizing temperature of a ferroelectric layer (3) (dielectric) to be used for the storage capacitor can be lowered by applying an extremely thin CeO2 layer (2) to a first platinum electrode layer (1) before depositing the ferroelectric layer (3). Continuously, in a treatment process, the dielectric layer (3) deposited in a noncrystalline state is crystallized at a temperature within the range from 590 to 620 deg.C. Next, a second electrode layer (4) is applied and the storage capacitor is completed.

公开(公告)号：JP2001273761A

公开(公告)日：2001-10-05

申请号：JP2001037522

申请日：2001-02-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACHHOFER HARALD ,  HANEDER THOMAS PETER ,  ULLMANN MARC ,  BRAUN GEORG ,  HONLEIN WOLFGANG

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To prevent a present state from being changed to a polarization state in which other ferroelectrioc transistor in other memory cell in a memory matrix cannot be discriminated, when a state is read out from a ferroelectric transistor or a state is stored in the ferroelectric transistor. SOLUTION: Threshold voltage of an other ferroelectric transistor in a memory matrix is increased by applying drain-substrate voltage to a ferroelectric transistor, when a state is read out from a ferroelectric transistor or a state is stored in the ferroelectric transistor.

公开(公告)号：WO0045441A3

公开(公告)日：2001-03-29

申请号：PCT/DE0000203

申请日：2000-01-25

Applicant: INFINEON TECHNOLOGIES AG ,  BACHHOFER HARALD ,  REISINGER HANS ,  HANEDER THOMAS PETER

Inventor： BACHHOFER HARALD ,  REISINGER HANS ,  HANEDER THOMAS PETER

IPC: H01L29/51 ,  H01L21/28

CPC classification number: H01L29/511

Abstract: The invention relates to a semiconductor device with a multiple dielectric, especially an ONO-triple dielectric, comprising a semiconductor substrate (10) of a first conduction type, a first doping area (20) of a second conduction type which is provided in said semiconductor substrate (10), a second doping area (30) of the second conduction type which is provided in the semiconductor substrate (10), a channel area (25) which is situated between the first and the second doping area (20, 30), a gate dielectric (40, 50, 60) which lies on top of the channel area (25) and which has at least three layers; and a gate terminal (70) which is provided on top of the gate dielectric (40, 50, 60). The bottom layer (40) of the gate dielectric (40, 50, 60) has an essentially smaller dielectric constant than the top layer (60) of the gate dielectric (40, 50, 60).

Abstract translation: 本发明提供了一种具有Mehrfachdielektrikum的半导体器件，特别是ONO Dreifachdielektrikum，包括：第一导电类型的半导体衬底（10）; 一个在设置于第二导电型的第一杂质区（20）的半导体衬底（10）; 一个在设置于第二导电型的第二杂质区（30）的半导体衬底（10）; 一个所述第一和第二杂质区之间躺在（20，30）沟道区（25）; 一个在所述沟道区（25）下面的栅极电介质（40，50，60），其具有至少三个层; 及以上的栅极端子（70）设置在栅极电介质（40，50，60）。 栅极电介质（40，50，60）的底部层（40）的介电常数比所述栅极电介质（40，50，60）的最上层（60）显着更小。

公开(公告)号：DE50112892D1

公开(公告)日：2007-10-04

申请号：DE50112892

申请日：2001-02-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACHHOFER HARALD ,  BRAUN GEORG ,  HANEDER THOMAS PETER ,  HOENLEIN WOLFGANG DR ,  ULLMANN MARC

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

公开(公告)号：DE19931125A1

公开(公告)日：2001-01-25

申请号：DE19931125

申请日：1999-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD ,  BRAUN GEORG

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L27/105

Abstract: The invention relates to a ferroelectric transistor which has two source/drain areas (13) and a channel area between them, in a semiconductor substrate (11), and in which a first dielectric intermediate layer (14) is situated on the surface of the channel area. Above said first dielectric intermediate layer (14) are a ferroelectric layer (15), a second dielectric intermediate layer (16) and a gate electrode (17). The second dielectric intermediate layer (16) reduces the leakage currents through the ferroelectric layer (15) to the interface between the first dielectric layer (14) and the ferroelectric layer, hereby improving the data management.

公开(公告)号：DE19947117B4

公开(公告)日：2007-03-08

申请号：DE19947117

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  REISINGER HANS ,  HANEDER THOMAS ,  BACHHOFER HARALD

IPC: H01L21/8247 ,  H01L29/78 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

公开(公告)号：DE59913465D1

公开(公告)日：2006-06-29

申请号：DE59913465

申请日：1999-07-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER PETER ,  REISINGER HANS ,  STENGL REINHARD ,  BACHHOFER HARALD ,  WENDT HERMANN ,  HOENLEIN WOLFGANG

IPC: H01L21/8247 ,  H01L29/786 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

公开(公告)号：DE19946437A1

公开(公告)日：2001-04-12

申请号：DE19946437

申请日：1999-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD ,  UNGER EUGEN

IPC: H01L21/8247 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

Abstract: The invention relates to a ferroelectric transistor comprising two source/drain regions (13) and a channel region arranged therebetween on a semiconductor substrate (11). A first dielectric intermediate layer (14) is located on the surface of the channel region and said layer contains Al2O3. A ferroelectric layer (15) and a gate electrode (16) are arranged above the first dielectric intermediate layer (14). A tunnel of compensatory charges from the channel region is suppressed in the first dielectric intermediate layer (14) by using Al2O3 in the first dielectric intermediate layer, thereby improving the data retention time.

公开(公告)号：DE10004392A1

公开(公告)日：2001-08-16

申请号：DE10004392

申请日：2000-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STEINLESBERGER GERNOT ,  HANEDER THOMAS ,  BACHHOFER HARALD

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/792 ,  H01L29/772

Abstract: A source/drain voltage is applied to the field effect transistor during injection of the charge carriers in the channel area of the field effect transistor with the purpose of achieving inhomogeneous distribution of the charge carrier in the channel area.

公开(公告)号：DE19931124C1

公开(公告)日：2001-02-15

申请号：DE19931124

申请日：1999-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/12 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.