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    21.
    发明专利
    未知

    公开(公告)号：DE10258780A1

    公开(公告)日：2003-07-10

    申请号：DE10258780

    申请日：2002-12-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FREY ULRICH ,  LEHMANN GUNTHER ,  WEINFURTNER OLIVER

    IPC: G11C17/18 ,  H03K17/00

    Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an "on" signal to the gate (38) of control transistor (36) only when a_"select_" signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.

    23.
    发明专利
    未知

    公开(公告)号：DE102007018316A1

    公开(公告)日：2007-10-31

    申请号：DE102007018316

    申请日：2007-04-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LEHMANN GUNTHER ,  DWIVEDI DEVESH ,  GUPTA SIDDHARTH

    IPC: G11C7/06

    Abstract: A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.

    26.
    发明专利
    未知

    公开(公告)号：DE102005009050B4

    公开(公告)日：2007-01-11

    申请号：DE102005009050

    申请日：2005-02-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LEHMANN GUNTHER ,  CHOSEROT VIANNEY ,  LARGUIER JEAN-YVES

    IPC: G11C17/16 ,  G11C7/06

    Abstract: A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.

    28.
    发明专利
    未知

    公开(公告)号：DE60109478T2

    公开(公告)日：2006-04-13

    申请号：DE60109478

    申请日：2001-10-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LEHMANN GUNTHER ,  DANIEL GABRIEL ,  FRANKOWSKY GERD

    IPC: G11C17/00 ,  G11C17/16 ,  G11C17/18

    Abstract: A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches. Each latch has a corresponding switch and a corresponding electrical fuse. A bit generator generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal. Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line connects to the electrical fuses. The blow voltage line is activated to blow fuses in accordance with programming data such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.

    29.
    发明专利
    未知

    公开(公告)号：DE60116774D1

    公开(公告)日：2006-04-06

    申请号：DE60116774

    申请日：2001-07-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LEHMANN GUNTHER ,  BRINTZINGER AXEL

    IPC: H01L23/525

    Abstract: A semiconductor device, in accordance with the present invention, includes a plurality of fuses disposed on a same level in a fuse bank. A plurality of conductive lines are routed through the fuse bank in between the fuses. A terminal via window is formed in a passivation layer over the plurality of conductive lines and over the plurality of fuses, the terminal via window being formed to expose the fuses in the fuse bank.

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