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    24.
    发明专利
    未知

    公开(公告)号：DE10059553A1

    公开(公告)日：2002-06-27

    申请号：DE10059553

    申请日：2000-11-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER RALF ,  WIRTH NORBERT ,  BENZINGER HERBERT

    IPC: G11C7/10 ,  G11C7/22

    Abstract: A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

    25.
    发明专利
    未知

    公开(公告)号：DE102004015269B4

    公开(公告)日：2008-03-27

    申请号：DE102004015269

    申请日：2004-03-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： VOLLRATH JOERG ,  GNAT MARCIN ,  SCHNEIDER RALF ,  CAMPENHAUSEN AUREL VON

    IPC: G11C29/00 ,  G01R19/165 ,  G11C5/14 ,  G11C11/4074 ,  G11C29/48 ,  G11C29/50 ,  H02H3/00

    Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

    27.
    发明专利
    未知

    公开(公告)号：DE10358038B4

    公开(公告)日：2006-05-18

    申请号：DE10358038

    申请日：2003-12-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER RALF ,  SCHROEDER STEPHAN ,  PROELL MANFRED ,  AUGE JUERGEN

    IPC: G11C11/407 ,  G11C7/00 ,  G11C16/04 ,  G11C29/44

    Abstract: An integrated circuit includes a programming circuit ( 10 ) for generating programming signals (PS 1 , . . . , PS 4 ) with a first input terminal (E 1 ) for applying a control voltage (ES), a second input terminal (E 2 ) for applying a reference voltage (Vref), a storage circuit ( 30 ) with programmable switches ( 35, . . . , 38 ) and output terminals (A 1 , . . . , A 4 ). The programming circuit in each case generates a programming signal (PS 1 , . . . , PS 4 ) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS 1 , . . . , PS 4 ) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches ( 35, . . . , 38 ). The programming state of the programmable switches can be read out via the output terminals (A 1 , . . . , A 4 ) of the integrated circuit. The integrated circuit enables the storage of external operating parameters of the integrated circuit.

    30.
    发明专利
    未知

    公开(公告)号：DE10161049C2

    公开(公告)日：2003-10-23

    申请号：DE10161049

    申请日：2001-12-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER RALF ,  BUCKSCH THORSTEN

    IPC: G01R31/30 ,  G01R31/3187 ,  G01R31/3193 ,  H01L21/66 ,  G06F11/26

    Abstract: An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.

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