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公开(公告)号:DE10247889A1
公开(公告)日:2004-04-22
申请号:DE10247889
申请日:2002-10-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: EVERSMANN BJOERN , PAULUS CHRISTIAN , THEWES ROLAND
IPC: G01N27/414 , G01N33/487
Abstract: A solid-state sensor assembly has a number of sensor components on or in a substrate. Each sensor component has an electrical signal converter coupled to a sensor element. Each sensor element produces a characteristic signal change in response to a sensor event. Each sensor has a an assembly maintaining a constant voltage applied to the signal converter, and a device to register the current flowing through the signal converter as a sensor signal. the signal converter is a field effect transistor whose gate is connected to the sensor element. The supply of electrical current is maintained at a constant value between the source-/drain connection in the field effect transistor. The electrical signal output is employed as the sensor signal. also claimed is an operating process.
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公开(公告)号:DE10228125A1
公开(公告)日:2004-01-22
申请号:DE10228125
申请日:2002-06-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEWES ROLAND , SCHIENLE MEINRAD , PAULUS CHRISTIAN , FREY ALEXANDER , HOLZAPFL BIRGIT , HOFMANN FRANZ
IPC: G01N27/403 , G01N33/487 , G01N33/50 , G01N27/02 , G01N27/416 , G01N33/483
Abstract: Biosensor array (700) comprising a substrate (601), on which biosensors (602) are mounted which have two connectors, is new. One of these (603) is connected to a control lead (605) while the other (604) is connected to a detector lead (606). A control unit supplies a signal to the desired biosensor and the detector lead feeds the signal produced by it to a processor. Independent claims are also included for: (a) a similar array in which control and detector leads are both replaced by signal leads (b) a method for operating the array with control and detector leads; and (c) a method for operating the array with signal leads.
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公开(公告)号:DE10226619A1
公开(公告)日:2004-01-15
申请号:DE10226619
申请日:2002-06-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BREDERLOW RALF , THEWES ROLAND , SAUERBREY JENS
IPC: G01K7/30
Abstract: The device has an RC element (103), a source of electrical charge carriers for charging the RC element's capacitor, a detection unit for detecting the value of a temperature-dependent electrical parameter of the RC element, a unit for determining the temperature of the RC element from the detected parameter value and a switch element (107) with which the capacitance (102) can be selectively coupled to the charge source or detection unit. Independent claims are also included for the following: (a) a calibration thermometer system with an inventive noise thermometer (b) a thermometer system with a noise thermometer (c) and a sensor arrangement with a noise thermometer.
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公开(公告)号:DE10218325A1
公开(公告)日:2003-11-13
申请号:DE10218325
申请日:2002-04-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BREDERLOW RALF , PAULUS CHRISTIAN , THEWES ROLAND
IPC: G01N27/447 , B81B7/00 , C12Q1/68 , G01N33/483
Abstract: Chip arrangement comprises a substrate (301), a channel (302) arranged on the substrate, electrodes (303, 304, 305) arranged in the channel, a control switching circuit (309) electrically coupled with the electrodes, and sensor elements (311, 312) arranged on or in the channel to acquire particles present in the surrounding region of the sensor element. An Independent claim is also included for a process for operating a chip arrangement.
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公开(公告)号:DE10204875C1
公开(公告)日:2003-02-27
申请号:DE10204875
申请日:2002-02-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor: LUYKEN JOHANNES , HOFMANN FRANZ , SIPRAK DOMAGOJ , BREDERLOW RALF , KREUPL FRANZ , PAULUS CHRISTIAN , THEWES ROLAND , WEBER WERNER , ELBE ASTRID , NEUHAUSER ROBERT , SCHEPERS JOERG
IPC: G06K19/073 , H01L23/58 , G06F12/14 , H01L51/10
Abstract: The IC chip has a layer structure with given electrical characteristics and a circuit stage for checking the latter electrical characteristics. The layer structure is provided by a resistance layer and 2 associated electrodes, the resistance layer provided as a molecular layer with an electrical resistance which can be switched both locally and globally between different conduction states. An Independent claim for a protection method for an IC chip is also included.
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公开(公告)号:DE10128574A1
公开(公告)日:2003-01-02
申请号:DE10128574
申请日:2001-06-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor: JENKNER MARTIN , THEWES ROLAND
Abstract: The invention relates to a device for handling, especially for positioning, selecting, transporting and/or fixing, vesicles (10) by means of a sieve element (6; 16; 26) comprising a plurality of pores (8; 28) for respectively receiving preferably a single vesicle (10), said pores (8; 28) having a pre-determined size and being arranged at pre-determined distances in relation to each other. The invention also relates to a method for handling and positioning vesicles (10). The vesicles (10) are supplied, in a solution, to a sieve element (6; 16; 26) in which pores (8; 28) are formed for receiving preferably single vesicles (10), the individual pores (8; 28) having a pre-determined size and position in the sieve element (6; 16; 26), and the vesicles (10) are deposited in the pores (8; 28).
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公开(公告)号:DE10124988A1
公开(公告)日:2002-12-12
申请号:DE10124988
申请日:2001-05-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEWES ROLAND , UNGER EUGEN
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公开(公告)号:DE59606804D1
公开(公告)日:2001-05-23
申请号:DE59606804
申请日:1996-06-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: PRANGE STEFAN , THEWES ROLAND , WOHLRAB ERDMUTE , WEBER WERNER
IPC: G06F7/53 , G06F7/00 , G06F7/50 , G06F7/501 , G06F7/506 , G06F7/52 , G06F7/527 , H03K19/08 , H03K19/20
Abstract: PCT No. PCT/DE96/00981 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 4, 1996 PCT Pub. No. WO96/42048 PCT Pub. Date Dec. 27, 1996In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are dimensioned in such a way that the cross-currents flowing through the transistors respectively represent a weighted summand of a first term of the threshold value equation. A second term of the threshold value equation is formed by a reference current representing the second term value. An evaluation unit compares an overall current, which results from the sum of cross-currents, with the reference current. The evaluation result is present at an output of the evaluation unit in the form of a stable output signal.
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公开(公告)号:DE19946490A1
公开(公告)日:2001-04-19
申请号:DE19946490
申请日:1999-09-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEWES ROLAND , WEBER WERNER , SCHWARZL SIEGFRIED
IPC: G11C11/14 , G11C11/15 , G11C11/56 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L27/22
Abstract: A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage cells, each storage cell having two intersecting electric conductors and a layer system comprising magnetic layers located at the intersection of the electric conductors. The memory is characterized in that the layer system is designated as a multilayer system with two or more magnetic layers, wherein at least two of the magnetic layers have a magnetization direction that can be set independently of one another. Further, the magnetization direction of the individual layers may be changed on the basis of the electric current flowing through the electric conductors.
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公开(公告)号:BR9813763A
公开(公告)日:2000-10-03
申请号:BR9813763
申请日:1998-12-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: JUNG STEFAN , THEWES ROLAND , WEBER WERNER
Abstract: Sensor elements are arranged in a hexagonal grid. A processor element in the form of a primitive automaton is assigned to each of the sensor elements in the grid. The processor elements are set up to perform algorithms which enable lines of a fingerprint to be simplified such that characteristic minutiae of the fingerprint (endings and branchings of the lines) can be extracted. The processor elements are embodied using CMOS/Neuron MOS threshold value logic or using CMOS/NMOS pass transistor logic. The image grid can be read out via read-out circuits as a matrix.
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