26.
    发明专利
    未知

    公开(公告)号:DE10128574A1

    公开(公告)日:2003-01-02

    申请号:DE10128574

    申请日:2001-06-13

    Abstract: The invention relates to a device for handling, especially for positioning, selecting, transporting and/or fixing, vesicles (10) by means of a sieve element (6; 16; 26) comprising a plurality of pores (8; 28) for respectively receiving preferably a single vesicle (10), said pores (8; 28) having a pre-determined size and being arranged at pre-determined distances in relation to each other. The invention also relates to a method for handling and positioning vesicles (10). The vesicles (10) are supplied, in a solution, to a sieve element (6; 16; 26) in which pores (8; 28) are formed for receiving preferably single vesicles (10), the individual pores (8; 28) having a pre-determined size and position in the sieve element (6; 16; 26), and the vesicles (10) are deposited in the pores (8; 28).

    28.
    发明专利
    未知

    公开(公告)号:DE59606804D1

    公开(公告)日:2001-05-23

    申请号:DE59606804

    申请日:1996-06-04

    Abstract: PCT No. PCT/DE96/00981 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 4, 1996 PCT Pub. No. WO96/42048 PCT Pub. Date Dec. 27, 1996In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are dimensioned in such a way that the cross-currents flowing through the transistors respectively represent a weighted summand of a first term of the threshold value equation. A second term of the threshold value equation is formed by a reference current representing the second term value. An evaluation unit compares an overall current, which results from the sum of cross-currents, with the reference current. The evaluation result is present at an output of the evaluation unit in the form of a stable output signal.

    29.
    发明专利
    未知

    公开(公告)号:DE19946490A1

    公开(公告)日:2001-04-19

    申请号:DE19946490

    申请日:1999-09-28

    Abstract: A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage cells, each storage cell having two intersecting electric conductors and a layer system comprising magnetic layers located at the intersection of the electric conductors. The memory is characterized in that the layer system is designated as a multilayer system with two or more magnetic layers, wherein at least two of the magnetic layers have a magnetization direction that can be set independently of one another. Further, the magnetization direction of the individual layers may be changed on the basis of the electric current flowing through the electric conductors.

    30.
    发明专利
    未知

    公开(公告)号:BR9813763A

    公开(公告)日:2000-10-03

    申请号:BR9813763

    申请日:1998-12-14

    Abstract: Sensor elements are arranged in a hexagonal grid. A processor element in the form of a primitive automaton is assigned to each of the sensor elements in the grid. The processor elements are set up to perform algorithms which enable lines of a fingerprint to be simplified such that characteristic minutiae of the fingerprint (endings and branchings of the lines) can be extracted. The processor elements are embodied using CMOS/Neuron MOS threshold value logic or using CMOS/NMOS pass transistor logic. The image grid can be read out via read-out circuits as a matrix.

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