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    22.
    发明专利
    未知

    公开(公告)号：DE102004045709B4

    公开(公告)日：2009-03-19

    申请号：DE102004045709

    申请日：2004-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： CLARA MARTIN ,  KOLHAUPT KLAUS ,  WIESBAUER ANDREAS ,  DI GIANDOMENICO ANTONIO

    IPC: H03F3/45 ,  H03F1/34

    Abstract: An amplifier and method of setting the amplifier is presented. The amplifier is set by setting a mean value between voltage values at first and second outputs of the amplifier. The mean value is pulled towards a certain voltage potential. A circuit node is coupled to the first and to the second output. The circuit node is connected, via at least one resistor and a respective switch, to the certain voltage potential assigned to the respective resistor.

    26.
    发明专利
    未知

    公开(公告)号：DE102005042710B4

    公开(公告)日：2007-04-26

    申请号：DE102005042710

    申请日：2005-09-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WIESBAUER ANDREAS ,  HERNANDEZ LUIS

    IPC: H03K5/04 ,  H03M1/10

    Abstract: Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter ( 15 ) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter ( 16 ) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator ( 18 ) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).

    27.
    发明专利
    未知

    公开(公告)号：DE102005041052B3

    公开(公告)日：2007-03-29

    申请号：DE102005041052

    申请日：2005-08-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SAN SEGUNDO BELLO DAVID ,  GIOTTA DARIO ,  WIESBAUER ANDREAS ,  POETSCHER THOMAS

    IPC: H04B3/08 ,  H03F3/217 ,  H04B3/36

    Abstract: A self-oscillating driver circuit includes a driver stage, a feedforward path which is coupled to an input of the driver stage, and a feedback path which couples an output of the driver stage to an input of the feedforward path. The feedforward path includes a feedforward filter which is designed as an active filter. In order to prevent an oscillatory state of the driver circuit at an unwanted frequency, it is proposed that an internal state variable of the feedforward filter be monitored and that the feedforward filter be reset if the value of the monitored internal state variable is outside a predefined range.

    28.
    发明专利
    未知

    公开(公告)号：DE102005026899B4

    公开(公告)日：2007-02-22

    申请号：DE102005026899

    申请日：2005-06-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STRAEUSNIGG DIETMAR ,  RAINER BERND ,  WIESBAUER ANDREAS ,  GAGGL RICHARD ,  CLARA MARTIN ,  HERNANDEZ LUIS

    IPC: H03M1/66 ,  H03M1/06

    Abstract: A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.

    29.
    发明专利
    未知

    公开(公告)号：DE10308946B4

    公开(公告)日：2006-02-16

    申请号：DE10308946

    申请日：2003-02-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GIOTTA DARIO ,  POETSCHER THOMAS ,  FERIANZ THOMAS ,  WIESBAUER ANDREAS ,  KOBAN RUEDIGER ,  FLEISCHHACKER CHRISTIAN

    IPC: H04L25/02 ,  H04L25/08

    Abstract: The signal (Vi) is coupled into the input (2), producing a line (4) signal (Vo) at the output (3). A digital amplifier (6) produces a pulse-width-modulated signal (Vd, id) from the input signal (Vi) or a superimposed signal (Vs). An analog amplifier (5) produces an analog signal (Ve', ia) at the output side from (Vi) or (Vs). The output sides of the amplifiers (5, 6) are so coupled, that through superimposition of the analog signal with the digital signal, the driven signal (Vo) results. Amplification of the analog amplifier is so matched with that of the digital amplifier, that dispersion and/or harmonic oscillations on the digital signal are at least reduced, after superimposition.

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